Memory architecture for solid state discs

• US 5,745,673 A
• Filed: 09/21/1995
• Issued: 04/28/1998
• Est. Priority Date: 09/21/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Grimani, Rodolfo, Di Zenzo, Maurizio
• Primary Examiner(s): Hua, Ly
• Application Number:
  US08/531,984
• Time in Patent Office: 950 Days
• Field of Search: 371/40.1, 371/40.2, 371/37.3, 395/182.04, 395/182.05, 395/445, 365/200, 365/230.01, 365/201
• US Class Current: 714/6.32
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G11B 20/1833 by adding special lists or symbols to the coded information G11B20/1806, G11B20/1866 take precedence
• CPC Class Codes: G11C 29/765 in solid state disks

Abstract

A solid state disc (SSD) Memory comprising the following functional blocks: a memory block (DATA ARRAY) wherein check data bytes are written; a transcoder memory block (SCRAMBLE RAM) which contains the table enabling the reallocation of the data matrix addresses, wherein redundant rows are included; a block (SCRAM DEC) for decoding the addresses of the decoder table; a logic block (FUSE LOGIC) to enable a step to be executed to locate any non-useable row and to substitute said redundant rows therefor; an error correction code (ECC) block for implementing the error correction algorithm; an input buffer block (LOGICAL ROW ADDRESS BUFFER) for storing the row addresses coming from the external bus; a non-volatile memory block, programmed during the test stage and available to a possible processor for handling the contents of the transcoder memory (SCRAMBLE RAM); a word counter block (WORD COUNTER) that is driven from the external clock signal (clock) and counts the number of the addressed words and generates the word addresses; two input and output buffer blocks (DATA IN/OUT) for the data to be written in or read out; a multiplexer block (MUX) by which the data stream is driven to the data memory (DATA ARRAY) or to the transcoder memory (SCRAMBLE RAM).

Claims

1. A memory comprising:

a first memory block in which data bytes are stored;

a second memory block which contains a transcoder table enabling reallocation of data addresses, wherein redundant rows are included;

a block for decoding the addresses of the transcoder table;

a fuse logic block to enable a step to be executed to locate non-useable rows and to substitute said redundant rows therefor;

an error correction code block for implementing an error correction algorithm;

a non-volatile memory fail map block, programmed during a test stage for storing addresses of non-useable rows in said first memory block for determining content of the transcoder table; and

a word counter block that is driven from a clock signal and counts the number of the addressed words and generates the word addresses.

2. The memory according to claim 1, further comprising;

an input logical row address buffer block for storing the row addresses coming from an external bus;

two input and output buffer blocks for the data to be written in or read out; and

a multiplexer block by which a data stream is driven to the first memory block or to the second memory block.

3. The memory according to claim 1, further including:

a refresh counter block to generate the addresses of both the first memory block and the second memory block;

an arbiter block that, by acting upon the refresh counter, controls the refresh operations and solves the conflict between the memory access and the memory refresh operations; and

a local oscillator block that provides for timing the arbiter block.

4. The memory according to claim 1, wherein the following signals operate the memory:

CE;

active low signal enabling the activation of a memory chip;

CLK;

a clocking signal which is enabled each time a byte arrives and in turn enables the word counter to count the addressed bytes;

INT;

an interrupt signal by which the error correction code (ECC) block indicates the existence of a non-corrigible error;

FAIL.MAP;

a signal, controlling said non-volatile memory block;

W;

a low active signal that enables data flow direction to be controlled, read/write;

SCRAM_-- EN;

a signal which enables a data bus to be connected either to the first or to the second memory.

5. The memory according claim 1, wherein the following buses are connected to the memory:

A0-A11;

12 bit buses used to supply a chip with the required 12 addresses,

I/O;

a 16 bit, bi-directional, data bus,

a further bus being provided for an external processor to access to a FAIL MAP block.

6. The memory according to claim 1, wherein the first memory block is a data array.

7. The memory according to claim 1, wherein the second memory block is a transcoder memory.

8. The memory according to claim 1 in the form of a Solid State Disc Memory.

9. A memory comprising:

a first memory block in which data bytes are stored wherein redundant rows are included;

a second memory block which contains a transcoder table enabling reallocation of data addresses;

a block for decoding the addresses of the transcoder table;

a non-volatile fail map memory block, programmed during a test stage for storing addresses of non-useable rows in said first memory block for determining content of the transcoder table memory; and

a word counter block that is driven from a clock signal and counts the number of the addressed words and generates the word addresses.

10. The memory according to claim 9, further comprising;

an error correction code block for implementing an error correction algorithm;

an input logical row address buffer block for storing the row addresses coming from an external bus;

two input and output buffer blocks for the data to be written in or read out; and

a multiplexer block by which a data stream is driven to the first memory block or to the second memory block.

11. The memory according to claim 9, further including:

a refresh counter block to generate the addresses of both the first memory block and the second memory block;

an arbiter block that, by acting upon the refresh counter, controls the refresh operations and solves the conflict between the memory access and the memory refresh operations; and

a local oscillator block that provides for timing the arbiter block.

12. The memory according to claim 9, wherein the first memory block is a data array.

13. The memory according to claim 9, wherein the second memory is a transcoder memory.

14. The memory according to claim 9 in the form of a Solid State Disc Memory.