Partitioned addressing apparatus for vector/scalar registers

• US 5,745,721 A
• Filed: 06/07/1995
• Issued: 04/28/1998
• Est. Priority Date: 12/29/1989
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: CRAY Incorporated (Hewlett-Packard Enterprise Company)
• Inventors: Spix, George A., Beard, Douglas R., Phelps, Andrew E., Woodmansee, Michael A., Blewett, Richard G., Lohman, Jeffrey A., Silbey, Alexander A., Simmons, Frederick J., Van Dyke, Don A.
• Primary Examiner(s): Eng, David Y.
• Application Number:
  US08/485,017
• Time in Patent Office: 1,056 Days
• Field of Search: 395/375, 395/775, 395/800, 395/405, 395/456, 395/479, 395/484, 395/497.04, 395/384
• US Class Current: 712/208
• CPC Class Codes: G06F 11/3632 of specific synchronisation aspects
• CPC Class Codes: G06F 15/17381 Two dimensional, e.g. mesh, torus
• CPC Class Codes: G06F 15/8076 Details on data register access
• CPC Class Codes: G06F 15/8092 Array of vector units
• CPC Class Codes: G06F 8/433 Dependency analysis; Data or control flow analysis
• CPC Class Codes: G06F 8/45 Exploiting coarse grain parallelism in compilation, i.e. parallelism between groups of instructions
• CPC Class Codes: G06F 9/30021 Compare instructions, e.g. Greater-Than, Equal-To, MINMAX
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30094 Condition code generation, e.g. Carry, Zero flag
• CPC Class Codes: G06F 9/3013 according to data content, e.g. floating-point registers, address registers
• CPC Class Codes: G06F 9/30138 Extension of register space, e.g. register cache
• CPC Class Codes: G06F 9/30141 Implementation provisions of register files, e.g. ports
• CPC Class Codes: G06F 9/30149 of variable length instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3804 for branches, e.g. hedging, branch folding
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3834 Maintaining memory consistency
• CPC Class Codes: G06F 9/3836 : Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06F 9/3838 : Dependency mechanisms, e.g. register scoreboarding
• CPC Class Codes: G06F 9/3846 : using static prediction, e.g. branch taken strategy
• CPC Class Codes: G06F 9/3856 : Reordering of instructions, e.g. using queues or age tags
• CPC Class Codes: G06F 9/3858 : Result writeback, i.e. updating the architectural state or memory
• CPC Class Codes: G06F 9/3875 : Pipelining a single stage, e.g. superpipelining
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A scalar/vector processor capable of concurrent scaler and vector operations includes scalar resources to process scalar instructions, and vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions. The scalar resources include scalar registers, and the vector resources include vector registers. Decoding means decodes each of a number of address fields. Each field represents a register address to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below a selected moveable address value within a range of addresses encompassed by the address field.

Claims

1. A scalar/vector processor capable of concurrent scaler and vector operations comprising:

scalar resources for processing scalar instructions, wherein the scalar resources including scalar registers;

vector resources adapted to be operated concurrently with the scalar resources and with one another to process vector instructions, wherein the vector resources include vector registers;

means for selecting a moveable address boundary from a range of address value encompassed by each of a number of address fields, each address field representing a register address of one of the scalar or vector registers; and

means for decoding each of the number of address fields to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below the selected moveable address boundary.

2. A method of operating a scalar/vector processor capable of concurrent scaler and vector operations, the method comprising:

processing scalar instructions with scalar resources having scalar registers;

processing vector instructions with vector resources adapted to be operated concurrently with the scalar resources, wherein the vector resources include vector registers;

selecting a moveable address boundary from a range of address values encompassed by each of a number of address fields, each address field representing a register address of one of the scalar or vector registers; and

decoding each of the number of address fields to access alternatively one of the scalar registers or one of the vector registers depending on a value of the register address being above or below the selected moveable address boundary.