Computer system including system controller with a write buffer and plural read buffers for decoupled busses

• US 5,745,732 A
• Filed: 11/15/1994
• Issued: 04/28/1998
• Est. Priority Date: 11/15/1994
• Status: Expired due to Term

• Current Assignee: Ravikrishna V. Cherukuri, Rozario, Ranjit J.
• Original Assignee: Ravikrishna V. Cherukuri, Rozario, Ranjit J.
• Inventors: Rozario, Ranjit J., Cherukuri, Ravikrishna V.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): KIM, HONG CHONG
• Application Number:
  US08/340,132
• Time in Patent Office: 1,260 Days
• Field of Search: 395/458, 395/476, 395/477, 395/478, 395/485, 395/495, 395/872, 395/876, 395/877, 395/840, 395/841, 395/847, 395/306, 395/308, 395/250, 395/474
• US Class Current: 711/168
• CPC Class Codes: G06F 12/0835 for main memory peripheral accesses (e.g. I/O or DMA)

Abstract

A computer system includes a processor having a cache memory and coupled to a system controller through a processor bus, a main memory coupled to the system controller through a dedicated memory bus, and a local bus master coupled to the system controller through a local bus. The system controller includes a write register and a read register that form a first path for coupling bus signals between the processor bus and main memory, and the system controller also includes a second read register that with the write buffer forms a second path to the main memory for coupling bus signals between the local bus and main memory. The first and second paths of the system controller decouple the processor and local buses, allowing processor-cache operations to proceed concurrently with operations between the local bus master and main memory. The first and second read buffers are fully snooped and implement replacement schemes that allow them to function as caches for the the processor and the local bus master, respectively, and a snoop tag register in the system controller stores recently snooped main memory addresses to eliminate redundant snoop cycles to the processor.

Claims

1. A virtual, multi-ported memory for facilitating concurrent operations in a computer system having multiple buses, the virtual, multi-ported memory comprising:

a single-ported main memory device;

a memory controller coupled to the main memory device for reading and writing memory locations in the main memory device responsive to signals from buffers;

a write buffer coupled between the memory controller and the multiple buses of the computer system, for buffering write signals between the multiple buses and the memory controller;

a first read buffer coupled between the memory controller and a first bus of the multiple buses for buffering read signals between the first bus and the memory controller and for snooping write signals to the write buffer; and

a second read buffer coupled between the memory controller and a second bus of the computer system for buffering read signals between the second bus and the memory controller and for snooping write signals to the write buffer.

2. The virtual, multi-ported memory of claim 1, further comprising a third read buffer coupled between the memory controller and a third bus of the multiple buses for buffer read signals between the third bus and the memory controller.

3. The virtual, multi-ported memory of claim 2, further comprising a memory arbitration unit coupled between the memory controller and the write and mad buffers, for regulating access to the memory controllers by the write and read buffers according to a first priority scheme.

4. The virtual, multi-ported memory of claim 3, further comprising a bus arbitration unit coupled to the multiple buses, read buffers, and write buffer for regulating access to the read buffers and write buffers according to a second priority scheme.

5. The virtual, multi-ported memory of claim 4, further comprising a bus controller coupled to the bus arbitration unit and the third bus for coupling bus control signals to the third bus and wherein data and address lines of the third bus are coupled to data and address lines of the second bus.

6. The virtual, multi-ported memory of claim 5, further comprising:

a first bus interface for coupling the write buffer and the first read buffer to the first bus; and

a second bus interface for coupling the write buffer and the second read buffer to the second bus and for coupling the write buffer and the third read buffer to the data and address lines of the third bus.

7. The virtual, multi-ported memory of claim 4, in which the first read buffer implements a data replacement protocol for prefetching data from main memory prior to receiving a read signal requesting the prefetched data.

8. The virtual, multi-ported memory of claim 7, in which the second read buffer implements a data replacement protocol for prefetching data from main memory prior to receiving a read signal requesting the prefetched data.

9. The virtual, multi-ported memory of claim 8, wherein the third read buffer implements a data replacement protocol for prefetching data from main memory prior to receiving a read signal requesting the prefetched data.

10. The virtual, multi-ported memory of claim 9, wherein a default condition of the first priority scheme allows the memory controller to process read signals from the read buffers prior to processing write requests from the write buffer.

11. The virtual, multi-ported memory of claim 9, wherein the first, second, and third read buffers are coupled to snoop write signals to the write buffer and wherein the first priority scheme allows the memory controller to process a write signal from the write buffer prior to processing a read signal from the first, second, and third buffers when the write signal is directed to an address in main memory that is the same as a read signal in one of first, second, or third read buffers.

12. A system controller for use in a computer system that includes a main memory, a central processor unit with a cache memory, a processor bus, and a local bus, the system controller comprising:

a first bus interface for translating bus signals between the processor bus and the system controller;

a second bus interface for translating bus signals between the local bus and the system controller;

a memory controller for providing control signals to the main memory, responsive to the receipt of read and write bus signals;

a write buffer coupled between the first bus interface and the memory controller and between the second bus interface and the memory controller, for buffering write bus signals that are applied to the first and second bus interfaces, respectively, to the memory controller;

a first read buffer coupled between the first bus interface and the memory controller for buffering read signals between the first bus interface and the memory controller, the first bus interface, the write buffer, and the first read buffer forming a first path to the memory controller; and

a second read buffer coupled between the second bus interface and the memory controller for buffering read bus signals between the second bus interface and the memory controller;

the second bus interface, the write buffer, and the second read buffer forming a second path to the memory controller that is decoupled from the first path to the memory controller formed by the first bus interface, the write buffer, and the first read buffer.

13. The system controller of claim 12, further comprising an inter-buffer interface coupled between the first and second bus interfaces, for translating bus signals between the first and second bus interfaces.

14. The system controller of claim 13, further comprising a bus arbitration controller coupled to the first and second bus interfaces for regulating control of the processor and local buses by bus masters on the processor and local buses in accordance with a priority scheme.

15. The system of claim 14, further comprising:

a third read buffer coupled between the second bus interface and the memory controller;

a bus controller coupled to the bus arbitration controller; and

wherein the computer system also includes an expansion bus that is coupled to the system controller through the local bus and to the bus controller, the expansion bus coupling signals between bus masters on the expansion bus and main memory and bus masters on the processor and local buses responsive to control signals from the bus controller.

16. The system controller of claim 15, further comprising:

a peripheral interface coupled to the bus arbitration controller; and

wherein the computer system also includes a peripheral controller that is coupled to the system controller through the expansion bus and the peripheral interface for providing direct memory access between peripheral devices on the expansion bus and main memory and between peripheral devices on the expansion bus and a memory slave on the local bus, responsive to control signals from the bus controller and the peripheral interface.

17. The system controller of claim 14, further comprising a memory arbitration controller coupled to the memory controller, the write buffer, and the first, second, and third read buffers, for regulating access to the memory controller from the read and write buffers according to a second priority scheme.

18. The system controller of claim 17, wherein a default condition of the second priority scheme allows the memory controller to process read signals from the read buffers prior to processing write requests from the write buffer.

19. The system controller of claim 18, wherein the first, second, and third read buffers are coupled to snoop write signals to the write buffer and wherein the second priority scheme allows the memory controller to process a write signal from the write buffer prior to processing a read signal from the first, second, and third buffers when the write signal is directed to an address in main memory that is the same as a read signal in one of first, second, or third read buffers.

20. The system controller of claim 19, further comprising a snoop control unit for coupling memory addresses asserted by bus masters on the first and expansion buses to the processor bus, for maintaining coherence between the data in the cache memory of the processor and the data in the read and write buffers of the system controller.

21. The system controller of claim 20, further comprising:

a snoop cross-over line coupled between the first bus interface and the first, second, and third buffers, for coupling selected data written to the write buffer by the processor to the read buffers; and

wherein the processor implements a MESI cache coherency protocol to identify selected data in the cache memory for immediate writing back to main memory, the snoop cross over line providing the selected data to a read buffer processing a read signal for the selected data.

22. A multi-bus computer system comprising:

a central processor having a cache memory;

a processor bus coupled to the central processor for coupling us signals to and from the central processor;

a local bus;

a main memory; and

a system controller coupled to the processor and local buses and the main memory for coupling bus signals between the processor and local buses and between main memory device and the processor and local buses, the system controller comprising;

a first bus interface for translating bus signals between the processor bus and the system controller;

a second bus interface for translating bus signals between the local bus and the system controller;

a memory controller for providing control signals to the main memory, responsive to the receipt of read and write bus signals;

a write buffer coupled between the first bus interface and the memory controller and between the second bus interface and the memory controller, for buffering write bus signals that are applied to the first and second bus interfaces, respectively, to the memory controller;

a first read buffer coupled between the first bus interface and the memory controller for buffering read signals between the first bus interface and the memory controller, the first bus interface, the write buffer, and the first read buffer forming a first path to the memory controller; and

a second read buffer coupled between the second bus interface and the memory controller for buffering read bus signals between the second bus interface and the memory controller, the second bus interface, the write buffer, and the second read buffer forming a second path to the memory controller that is decoupled from the first path to the memory controller formed by the first bus interface, the write buffer, and the first read buffer.

23. The multi-bus computer system of claim 22, wherein the system controller further comprises an inter-buffer interface coupled between the first and bus interfaces, for translating bus signals between the first and second bus interfaces.

24. The multi-bus computer system of claim 23, wherein the system controller further comprises a bus arbitration controller coupled to the first and second bus interfaces for regulating control of the processor and local buses by bus masters on the processor and local buses in accordance with a priority scheme.

25. The multi-bus computer system of claim 24, further comprising:

an expansion bus that is coupled to the system controller through the local bus; and

wherein the system controller further comprises a third read buffer coupled between the second bus interface and the memory controller and a bus controller coupled to the bus arbitration controller and the expansion bus, for coupling signals between bus masters on the expansion bus and main memory and bus masters on the processor and local buses responsive to control signals from the bus controller.

26. The multi-bus computer system of claim 24, further comprising:

a peripheral controller that is coupled to the system controller through the expansion bus; and

wherein the system controller further comprises a peripheral interface coupled to the bus arbitration controller and the peripheral controller, for providing direct memory access between peripheral devices on the expansion bus and main memory and between peripheral devices on the expansion bus and a memory slave on the local bus, responsive to control signals from the bus controller and the peripheral interface.

27. The multi-bus computer system of claim 24, wherein the system controller further comprises a memory arbitration controller coupled to the memory controller, the write buffer, and the first, second, and third read buffers, for regulating access to the memory controller from the read and write buffers according to a second priority scheme.