Method and system for programming a gate array using a compressed configuration bit stream
First Claim
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1. A programmable logic circuit comprising:
- a plurality of programmable logic resources;
a configuration input; and
a generalized data decompression engine having a compressed input and a decompressed output, said compressed input being coupled to said configuration input and said decompressed output being coupled to said plurality of programmable logic resources to provide programming thereof,wherein said generalized data decompression engine comprises a Lempel-Ziv decompression engine.
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Abstract
A generalized data decompression engine is incorporated within a field programmable gate array ("FPGA"). The generalized data decompression engine uses a general purpose data decompression technique such as, for example, a Lempel-Ziv type technique. During operation, a compressed configuration bit stream is received by the generalized data decompression engine in the FPGA and is decompressed thereby. A resultant decompressed configuration bit stream is then used to program logic cells within the FPGA.
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Citations
39 Claims
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1. A programmable logic circuit comprising:
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a plurality of programmable logic resources; a configuration input; and a generalized data decompression engine having a compressed input and a decompressed output, said compressed input being coupled to said configuration input and said decompressed output being coupled to said plurality of programmable logic resources to provide programming thereof, wherein said generalized data decompression engine comprises a Lempel-Ziv decompression engine. - View Dependent Claims (2)
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3. A programmable logic circuit comprising:
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a plurality of programmable logic resources; a configuration input; a generalized data decompression engine having a compressed input and a decompression output, said compressed input being coupled to said configuration input and said decompressed output providing direct run-time personalization of said plurality of programmable logic resources; and a configuration memory for said direct run-time personalization of said plurality of programmable logic resources said configuration memory also comprising a history buffer of said generalized data decompression engine. - View Dependent Claims (4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. A programmable logic circuit comprising:
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a plurality of programmable logic resources; a configuration input; a generalized data decompression engine having a compressed input and a decompressed output, said compressed input being coupled to said configuration input and said decompressed output being coupled to said plurality of programmable logic resources to provide programming thereof, wherein said generalized data decompression engine comprises serial processing logic and wherein said compressed input of said generalized data decompression engine comprises a serial data input; and a parallel to serial converter including a parallel address output, a parallel data input and a serial data output, said serial data output being coupled to said serial data input of said generalized data decompression engine, said parallel address output and said parallel data input adapted to couple to a parallel organized memory. - View Dependent Claims (17, 18, 19)
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20. A programmable logic circuit comprising:
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a plurality of programmable logic resources; a configuration input; and a generalized data decompression engine having a compressed input and a decompressed output, said compressed input being coupled to said configuration input and said decompressed output being coupled to said plurality of programmable logic resources to provide programming thereof, wherein said circuit comprises an integrated circuit chip having a floorplan, said floorplan having an elongated region separating groups of said plurality of programmable logic resources, said generalized data decompression engine being within said elongated region. - View Dependent Claims (21)
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22. A method for programming a programmable logic circuit comprising a plurality of programmable logic resources, said method comprising the steps of:
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(a) receiving a compressed configuration; (b) decompressing said compressed configuration using a generalized data decompression technique to produce a decompressed configuration; and (c) programming said plurality of logic resources using said decompressed configuration, wherein said decompressing step (b) comprises decompressing said configuration using a Lempel-Ziv decompression technique. - View Dependent Claims (23)
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24. A method for programming a programmable logic circuit comprising a plurality of programmable logic resources, said method comprising the steps of:
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(a) receiving a compressed configuration; (b) decompressing said compressed configuration using a generalized data decompression technique to produce a decompressed configuration; and (c) programming said plurality of logic resources using said decompressed configuration, wherein said programmable logic circuit further comprises a configuration memory for direct run-time personalization of said plurality of programmable logic resources, said method further including accessing said configuration memory as a history buffer during said decompressing step (b). - View Dependent Claims (25, 26, 27, 28, 29, 30, 31, 32, 33, 34)
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35. A method for programming a programmable logic circuit comprising a plurality of programmable logic resources said method comprising the steps of:
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(a) receiving a compressed configuration; (b) decompressing said compressed configuration using a generalized data decompression technique to produce a decompressed configuration; and (c) programming said plurality of logic resources using said decompressed configuration, wherein said compressed configuration comprises a serial bit stream, said programmable logic circuit further comprising a parallel to serial converter including a parallel address output, a parallel data input and a serial data output for generating said serial bit stream, said parallel address ouptut and said parallel data input adapted to couple to a parallel organized memory, said method further including serializing said parallel data input to produce said serial bit stream. - View Dependent Claims (36, 37, 38)
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39. A method for reducing the amount of configuration information needed to configure a programmable logic circuit comprising the steps of:
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(a) compressing a configuration for the programmable logic circuit using a generalized compression technique to produce a compressed configuration; and (b) transferring said compressed configuration to a configuration storage device that facilitates loading of the programmable logic circuit, wherein said compressing step (a) comprises compressing said configuration with a Lempel-Ziv compression technique.
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Specification