Method for repairing defective electrical connections on multi-layer thin film (MLTF) electronic packages

• US 5,747,095 A
• Filed: 02/14/1997
• Issued: 05/05/1998
• Est. Priority Date: 12/21/1995
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Swaminathan, Madhavan, Prasad, Chandrika, McDonald, James, McAllister, Michael, Perfecto, Eric Daniel, Robbins, Gordon J., Prasad, Keshav, White, George Eugene
• Primary Examiner(s): PIANALTO, BERNARD D
• Application Number:
  US08/800,945
• Time in Patent Office: 445 Days
• Field of Search: 427/8, 427/96, 427/123, 427/404, 427/261, 427/282
• US Class Current: 427/8
• CPC Class Codes: H01L 21/485 Adaptation of interconnections, e.g. engineering charges, repair techniques
• CPC Class Codes: H01L 23/5382 Adaptable interconnections, e.g. for engineering changes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]
• CPC Class Codes: H05K 2203/162 Testing a finished product, e.g. heat cycle testing of solder joints
• CPC Class Codes: H05K 3/0082 characterised by the exposure method of radiation-sensitive masks
• CPC Class Codes: H05K 3/225 Correcting or repairing of printed circuits H05K1/0292, H05K3/222, H05K3/288, H05K3/4685 take precedence
• CPC Class Codes: H05K 3/4644 by building the multilayer layer by layer, i.e. build-up multilayer circuits making via holes in the insulating layers H05K3/0011; special circuit boards as base or core whereon the multilayer is built H05K3/4602

Abstract

A multi-layer thin film structure having defined repair lines thereon and a method for repairing interconnections in the multi-layer thin film structure (MLTF) and/or making engineering charges (EC) are provided. The method comprises determining any interconnection defects in the MLTF at a thin film layer adjacent the top metal layer of the structure, using lithography, e.g., direct write expose technology, to define the top surface connections needed to repair the interconnections and/or make EC'"'"'s, and forming the top surface metallization and repair lines using additive or substractive metallization techniques.

Claims

1. A method for repairing interconnections of multi-layer thin film structures or making engineering changes to the structures which structures comprise a series of layers comprising a dielectric having plated metal thereon in the form of wiring and via interconnections to the next layer and a top layer of the structure which has interconnecting vias to the lower layers and corresponding chip connection pads comprising the steps of:

building the multi-layer thin film structure layer by layer up to a layer adjacent to the top layer;

testing and/or inspecting the layer adjacent the top layer to determine interconnection faults in the multi-layer thin film structure;

forming the top layer comprising a dielectric and defining, vias, pads and via-pad connecting lines metallization;

depending on the defects determined in the multi-layer thin film structure obtained by testing the layer adjacent the top layer, defining the repair lines on the top surface needed to cure the defects and/or make engineering changes; and

forming the metallization and repair lines on the top surface to cure the defects and/or make engineering changes.

2. The method of claim 1 wherein the repair lines are defined using a direct write tool controlled by an algorithm that analyzes the test data and determines the repair wiring needed for the multi-layer thin film structure.

3. The method of claim 2 wherein the metallization and repair lines are formed on the top dielectric layer by applying a layer of metal, applying a layer of photoresist, using the direct write tool to define the repair lines by exposing the resist layer based on an algorithm using the data obtained, developing the resist, plating the developed structure, and stripping the resist and metal layer.

4. The method of claim 1 wherein the top surface metallization is formed using a fixed mask.

5. The method of claim 1 wherein each thin film layer is tested and/or inspected after its fabrication to determine intralevel defects and repairing any such defects before the next layer is formed.

6. A method of forming a multi-layer thin film structure which comprises a series of layers comprising a dielectric having metal thereon in the form of wiring and via interconnections and a top surface layer of the structure which has vias, chip connection pads and via pad connection straps and defined metal repair lines thereon comprising the steps of:

building a multi-layer thin film structure, having a top surface metal layer, layer by layer up to a layer adjacent to the top surface metal layer of the structure;

electrically testing and/or inspecting the layer adjacent to the top surface metal layer and determining faulty interconnections;

determining the best metal line routes to repair faulty interconnections and/or making engineering changes;

building the top surface layer and defining the metal repair lines thereon; and

forming vias, via connection straps, chip connection pads and metal repair and/or engineering change lines on the top surface layer.

7. The method of claim 6 wherein the metal repair and/or engineering change lines are defined by a direct write exposure tool controlled by an algorithm that analyzes the test data and determines the repair and/or engineering change wiring needed.

8. The method of claim 7 wherein the via connection straps and repair and/or engineering change lines are defined by a direct write exposure tool controlled by an algorithm that analyzes the test data and determines the connection straps, repair and/or engineering change wiring needed and does not need a strap line deletion operation.

9. The method of claim 6 wherein the structure is repaired and/or engineering change are made without adding any additional conductors after the top surface metal layer has been formed.

10. The method of claim 6 wherein the top surface metal features are formed using subtractive or additive metallization techniques.