Robust end-point detection for contact and via etching

• US 5,747,380 A
• Filed: 02/26/1996
• Issued: 05/05/1998
• Est. Priority Date: 02/26/1996
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Jang, Syun-Ming
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): Everhart, Caridad
• Application Number:
  US08/606,833
• Time in Patent Office: 799 Days
• Field of Search: 437/195, 437/191, 437/8, 437/186, 437/228, 437/235, 437/245, 437/225, 438/599, 438/637, 438/926, 438/942
• US Class Current: 438/599
• CPC Class Codes: B24B 37/013 Devices or means for detecting lapping completion
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 22/26 Acting in response to an ongoing measurement without interruption of processing, e.g. endpoint detection, in-situ thickness measurement endpoint detection arrangements in CMP apparatus B24B37/013, in discharge apparatus H01J37/32
• CPC Class Codes: Y10S 438/926 Dummy metallization

Abstract

A method for improving the end-point detection for contact and via etching is disclosed. The disclosure describes the deliberate addition of dummy patterns in the form of contact and via holes to the regular functional holes in order to increase the amount of etchable surface area. It is shown that, one can then take advantage of the marked change in the composition of the etchant gas species that occurs as soon as what was once a large exposed area has now been consumed through the etching process. This then gives a strong and robust signal for the end of the etching process. This in turn results in better controlled and more reliable product. It is also indicated that with the full uniform pattern of the via layers now possible, the chemical/mechanical polishing process becomes much less pattern sensitive.

Claims

1. A method for improving the end-point detection for contact hole etching in multilayer metallurgy of submicron IC devices comprising the steps of:

providing a semiconductor substrate having devices formed within its surface;

depositing interconnect metal onto said substrate surface;

patterning local interconnect regions and dummy regions on said substrate;

depositing oxide layer over said substrate and covering said interconnect metal under thereof;

etching contact holes and dummy holes through the thickness of said oxide layer; and

depositing first level metal into contact and dummy holes.

2. The method of claim 1, wherein said devices have polysilicon gates.

3. The method of claim 1, wherein the local interconnect metal is patterned to have isolated metallized dummy regions.

4. The method of claim 3, wherein said interconnect and dummy regions are polysilicon.

5. The method of claim 1, wherein said dielectric oxide is deposited over said metal layer in a PECVD reactor.

6. The method of claim 5, wherein the thickness of said oxide layer is between about 5,000 to 10,000 Angstroms.

7. The method of claim 1, wherein said dielectric is patterned with contact holes and dummy holes over underlying contact regions and dummy regions, respectively.

8. The method of claim 1, wherein said dielectric is dry-etched to form contact openings.

9. The method of claim 8, wherein said contact openings are comprised of dummy openings and openings that are functional.

10. The method of claim 1, wherein first level metal is deposited onto the surface having contact and dummy holes.

11. The method of claim 10, wherein the thickness of said metal is in between about 3,000 to 8,000 Angstroms.

12. The method of claim 10, wherein said metal makes contact with silicon wherever contact holes have access to silicon.

13. The method of claim 10, wherein said metal makes contact with dummy metal through dummy holes that are positioned over dummy metal regions.

14. A method for improving the end-point detection for via hole etching in multilayer metallurgy of submicron IC devices comprising the steps of:

providing a semiconductor substrate having a first level of metallization on its surface;

depositing an oxide coating over said substrate surface;

etching via holes and dummy holes through the thickness of said oxide coating; and

depositing second level metal into said via and dummy holes.

15. The method of claim 14, wherein said oxide is deposited over the first metal layer in a PECVD reactor.

16. The method of claim 15, wherein the thickness of said oxide is in between about 5,000 to 10,000 Angstroms.

17. The method of claim 14, wherein said dielectric is patterned with via holes and dummy holes over underlying via regions and dummy regions, respectively.

18. The method of claim 15, wherein said oxide is dry-etched to form via openings.

19. The method of claim 18, wherein said vias are comprised of functional vias and dummy vias.

20. The method of claim 14, wherein second metal is deposited onto the surface having the via openings.

21. The method of claim 14, wherein the first metal is patterned to have isolated metallized dummy regions.

22. The method of claim 20, wherein the second metal makes contact with the first metal wherever via holes have access to the first metal.

23. The method of claim 20, wherein said second metal makes contact with dummy metal wherever via holes have access to isolated metallized regions.

24. A method of forming an interconnecting metallization system comprising the steps of:

providing a semiconductor substrate having devices formed within its surface;

depositing interconnect metal layer onto said substrate surface;

forming active and dummy metal interconnect regions on said interconnect metal layer;

depositing first oxide layer covering said interconnect metal layer on said substrate surface;

forming contact holes and dummy contact holes through said first oxide layer, wherein said respective holes reach underlying said active and said dummy interconnect regions, respectively;

depositing first level metal;

forming active and dummy first metal regions on said first level metal;

depositing second oxide layer covering said first level metal on said substrate surface;

forming via holes and dummy via holes through said second oxide layer, wherein said respective holes reach underlying said active and said dummy first level metal regions, respectively;

depositing second level metal; and

depositing passivation layer.