Epitaxial overgrowth method and devices

• US 5,747,842 A
• Filed: 06/07/1995
• Issued: 05/05/1998
• Est. Priority Date: 04/30/1993
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Plumton, Donald L.
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/472,791
• Time in Patent Office: 1,063 Days
• Field of Search: 257/266, 257/279, 257/655
• US Class Current: 257/266
• CPC Class Codes: H01L 21/02433 Crystal orientation
• CPC Class Codes: H01L 21/02546 Arsenides
• CPC Class Codes: H01L 21/02576 N-type
• CPC Class Codes: H01L 21/02579 P-type
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/74 Making of localized buried regions, e.g. buried collector layers, internal connections substrate contacts
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 27/0629 in combination with diodes, or resistors, or capacitors
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/1066 Gate region of field-effect devices with PN junction gate
• CPC Class Codes: H01L 29/1075 of field-effect transistors
• CPC Class Codes: H01L 29/20 including, apart from doping materials or other impurities, only AIIIBV compounds
• CPC Class Codes: H01L 29/66318 Heterojunction transistors
• CPC Class Codes: H01L 29/66454 Static induction transistors [SIT], e.g. permeable base transistors [PBT]
• CPC Class Codes: H01L 29/66924 with an active layer made of a group 13/15 material H01L29/66446 takes precedence
• CPC Class Codes: H01L 29/7371 Vertical transistors
• CPC Class Codes: H01L 29/7722 using static field induced regions, e.g. SIT, PBT
• CPC Class Codes: H01L 29/8083 Vertical transistors SIT H01L29/7722

Abstract

A vertical field effect transistor (100) and fabrication method with buried gates; (104) having spaced apart gate fingers and connecting structure and overgrown with source and channel epilayer followed by a doping connection of the gate fingers and connecting structure.

Claims

1. A vertical field effect transistor, comprising:

(a) a plurality of parallel gate fingers buried in a semiconductor body containing dopands of a first conductivity type, said gate fingers containing only dopants of a second conductivity type opposite said first conductivity type;

(b) a connecting structure containing dopants only of said second conductivity type and buried in said body and spaced from said gate fingers; and

(c) a region of said body connecting said gate fingers to said connecting structure, said region containing dopants for both said first and said second conductivity types with the concentration of said dopants of said second conductivity type exceeding that of said dopants of said first conductivity type.

2. The transistor of claim 1, wherein:

(a) said gate fingers and said connecting structure are p type GaAs; and

(b) said body is n type GaAs.

3. The transistor of claim 2, wherein:

(a) said gate fingers and said connecting structure have dimensions characterized by formation from a planar layer by removal of portions of said planar layer.

4. The transistor of claim 3, wherein:

(a) the concentration of first conductivity type dopants in said body is greater in the portions between adjacent ones of said gate fingers than in the portion on one side of and adjacent to said planar layer.

5. The transistor of claim 4, further comprising:

(a) a metal contact to said portion of said body on said one side of said planar layer;

(b) a second metal contact to a second portion of said body on a side of said planar layer opposite said one side; and

(c) a third metal contact to said region which extends to a surface of said body.