Multi-chip module inductor structure

• US 5,747,870 A
• Filed: 06/08/1995
• Issued: 05/05/1998
• Est. Priority Date: 06/30/1994
• Status: Expired due to Fees

• Current Assignee: Mitel Semiconductor, Limited (Microchip Technology Incorporated)
• Original Assignee: Plessey Semiconductors Limited (Plessey Group Holdings Ltd.)
• Inventors: Pedder, David John
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): Cao, Phat X.
• Application Number:
  US08/483,462
• Time in Patent Office: 1,062 Days
• Field of Search: 257/531, 257/700, 257/714, 257/717, 257/737
• US Class Current: 257/531
• CPC Class Codes: H01F 17/0006 Printed inductances printed coils for dynamo-electric machines H02K3/26; printed circuits H05K
• CPC Class Codes: H01F 17/04 with magnetic core
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/29099 Material
• CPC Class Codes: H01L 2924/00013 Fully indexed content

Abstract

In a multichip module structure comprising a silicon, alumina or sapphire substrate carrying a plurality of layers of metallisation separated by polymer dielectric layers, with one or more inductors formed in the uppermost metallisation layer, a ferrite core for one of those inductors is located over the inductor and secured in position by flip chip solder bonding.

Claims

1. A multi-chip module inductor structure, comprising:

a substantially planar substrate of electrically insulating material;

a multilayer metallization/insulation structure formed on said substrate and comprising at least a lower metallization layer, a layer of electrically insulating material formed over said lower metallization layer, and an upper metallization layer formed over said layer of electrically insulating material;

an inductor defined in at least said upper metallization layer;

a substantially planar chip of ferrite material having upper and lower major surfaces;

a plurality of solder bond pads defined in said upper metallization layer and a like plurality of solder bond pads formed on said lower major surface of said chip of ferrite material; and

means, including a like plurality of solder bump connections, for attaching said chip of ferrite material over said planar inductor and in spaced relationship therewith.