Method of blocking bidirectional flow of current

• US 5,747,891 A
• Filed: 04/23/1996
• Issued: 05/05/1998
• Est. Priority Date: 11/30/1993
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K.
• Primary Examiner(s): Shoop, Jr., William M.
• Assistant Examiner(s): KAPLAN, JONATHAN STUART
• Application Number:
  US08/636,367
• Time in Patent Office: 742 Days
• Field of Search: 307/43, 307/64, 307/65, 307/66, 307/85, 307/86, 307/87, 307/112, 307/113, 307/115, 307/116, 307/125, 307/130, 307/131, 257/336, 257/402, 257/392, 257/655
• US Class Current: 307/87
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: H02J 1/10 Parallel operation of dc sources
• CPC Class Codes: H02J 7/0024 Parallel/serial switching of connection of batteries to charge or load circuit
• CPC Class Codes: H02J 7/0031 using battery or load disconnect circuits H02J9/002 takes precedence
• CPC Class Codes: H02J 7/0034 using reverse polarity correcting or protecting circuits mechanical means of polarity protection H02J7/0045
• CPC Class Codes: H02J 9/061 for DC powered loads
• CPC Class Codes: H03K 17/0822 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 17/6874 in a symmetrical configuration
• CPC Class Codes: H03K 17/693 Switching arrangements with several input- or output-terminals, e.g. multiplexers, distributors logic circuits H03K19/00; code converters H03M5/00, H03M7/00

Abstract

A bidirectional current blocking switch is disclosed. The switch includes a four-terminal MOSFET in which there is no source-body short. The voltages applied to the source and drain terminals are both higher than the voltage applied to the body terminal (for an N-channel) device so that the source-body and drain-body junction of the MOSFET never become forward-biased. The switch of this invention is particularly useful for switching a cascaded set of batteries in a portable computer.

Claims

1. A method of blocking a flow of current between a first terminal and a second terminal, respective voltages at the first and second terminals varying such that during a first time interval a first voltage at the first terminal is greater than a first voltage at the second terminal and during a second time interval a second voltage at the second terminal is greater than a second voltage at the first terminal, the method comprising the steps of:

providing a MOSFET, the MOSFET comprising a first region of a first conductivity type separated from a second region of the first conductivity type by a body region of a second conductivity type, the MOSFET further comprising a gate separated from a channel region of the body region by a dielectric layer, wherein neither the first region nor the second region is shorted by the body region;

conducting said first terminal to said first region;

connecting said second terminal to said second region;

maintaining the body region at at least one potential such that neither a PN junction between the first region and the body region nor a PN junction between the second region and the body region is forward-biased so as to conduct a current as the voltages at the first and second terminals vary;

biasing the gate so as to block a flow of current between the first and second regions in a first direction during the first time interval; and

biasing the gate so as to block a flow of current between the first and second regions in a second direction during the second interval.

2. The method of claim 1 comprising the further step of biasing the gate so as to allow a flow of current between the first and second regions in the first direction.

3. The method of claim 2 comprising the further step of biasing the gate so as to allow a flow of current between the first and second regions in the second direction.

4. The method of claim 3 wherein the method further comprises connecting the first region is to a first terminal and connecting the first terminal to a first power source.

5. The method of claim 4 wherein the method further comprises connecting the second region to a second terminal and connecting the second region to a second power source.

6. The method of claim 5 wherein the first power source comprises a battery.

7. The method of claim 6 wherein the second power source comprises an AC/DC converter.

8. The method of claim 5 wherein the first power source comprises a first battery and the second power source comprises a second battery.

9. The method of claim 5 comprising the further step of connecting the second terminal to a load.

10. The method of claim 9 wherein the step of biasing the gate so as to block a flow of current in the first direction is immediately followed by the step of biasing the gate so as to allow a flow of current the first direction, and wherein a transition time between the step of biasing the gate so as to block a flow of current in the first direction and biasing the gate so as to allow a flow of current the first direction is fast relative to a capacitive reaction time of the load.

11. The method of claim 5 comprising the further step of connecting the first terminal to a battery charger.

12. The method of claim 1 wherein the step of maintaining the body region at at least one potential comprises maintaining the body region at a constant potential.

13. The method of claim 12 wherein each of the first and second voltages at the first terminal and each of the first and second voltages at the second terminal is greater than or equal to the constant potential.

14. The method of claim 12 wherein the constant potential is ground.

15. The method of claim 14 wherein the steps of biasing the gate to block the flow of current in the first and second directions, respectively, comprise connecting the gate to ground.