Driver circuit

• US 5,748,016 A
• Filed: 03/20/1996
• Issued: 05/05/1998
• Est. Priority Date: 03/22/1995
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Kurosawa, Susumu
• Primary Examiner(s): Callahan, Timothy P.
• Assistant Examiner(s): LAM, TUAN THIEU
• Application Number:
  US08/618,778
• Time in Patent Office: 776 Days
• Field of Search: 327/108, 327/112, 327/379, 327/387, 327/389, 327/391, 327/534, 326/22-24, 326/31, 326/34, 326/23, 326/27
• US Class Current: 327/108
• CPC Class Codes: H01L 29/78606 with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device H01L29/78642, H01L29/78645 take precedence
• CPC Class Codes: H03K 19/0013 in field effect transistor circuits
• CPC Class Codes: H03K 19/00361 in field effect transistor circuits
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A driver circuit comprising (i) a pair of complementary MOS (CMOS) transistors connected in series and receiving an identical input signal, and (ii) a pair of control transistors changing a threshold voltage state of each of the pair of CMOS transistors by applying a plurality of voltages to a body terminal of each of the pair of CMOS transistors depending upon the ON/OFF state of each of the pair of CMOS transistors. Such a driver circuit is capable of reconciling a high-speed operation with a low power consumption under low power supply voltage conditions.

Claims

1. A driver circuit comprising:

a pair of complementary MOS (CMOS) transistors connected in series between power supply voltage value and ground voltage value and configured to receive an input signal; and

a pair of control transistors configured to receive said input signal and to change a threshold voltage state of each transistor of the pair of CMOS transistors by applying a plurality of voltages to body terminals of the pair of CMOS transistors depending upon an ON/OFF state of each transistor of the pair of CMOS transistors.

2. A driver circuit according to claim 1,

wherein said pair of control transistors apply the plurality of voltages in accordance with a voltage value applied to gate terminals of said pair of CMOS transistors.

3. A driver circuit according to claim 1,

wherein the plurality of voltages comprise a first and second voltage, and wherein when one of said pair of CMOS transistors is an n-channel transistor, the first voltage is an intermediate value between said supplied power supply voltage value and said ground voltage value, and the second voltage substantially is the same value as the supplied ground voltage value.

4. A driver circuit according to claim 1,

wherein the plurality of voltages comprise a first and second voltage, and wherein when one of said pair of CMOS transistors is a p-channel transistor, the first voltage is an intermediate value between said power supply voltage value and said ground voltage value, and the second voltage is substantially the same value as the power supply voltage value.

5. A driver circuit according to claim 1,

wherein said pair of control transistors have the same conductivity type as said pair of CMOS transistors;

and

at least one of the pair of control transistors further comprises,

a source connected to said body terminal of one of the pair of CMOS transistors,

a drain connected to a gate of said one of the pair of CMOS transistors, and

a gate connected to a gate voltage, wherein said gate voltage turns ON said at least one of the pair of control transistors.

6. A driver circuit according to claim 1,

wherein said pair of control transistors have the same conductivity type as said pair of CMOS transistors;

and

at least one of the pair of control transistors further comprises,

a source connected to said body terminal of one of the pair of CMOS transistors,

a drain connected to a drain of said one of the pair of CMOS transistors, and

a gate connected to a gate of said one of the pair of CMOS transistors.

7. A driver circuit according to claim 1, wherein said pair of CMOS transistors and said pair of control transistors are formed by SOI technology.

8. A driver circuit comprising:

a first MOSFET of a first conductivity type;

a second MOSFET of a second conductivity type connected in series to said first MOSFET, said first and second MOSFETs each having a gate terminal configured to receive an input signal;

a first control transistor configured to apply a first voltage to a body terminal of said first MOSFET in an ON state in order to hold said first MOSFET in a low threshold voltage state, and configured to apply a second voltage to said body terminal of said first MOSFET in an OFF state in order to hold said first MOSFET in a high threshold voltage state; and

a second control transistor configured to apply the first voltage to a body terminal of said second MOSFET in an ON state in order to hold said second MOSFET in the low threshold voltage state, and configured to apply a third voltage to said body terminal of said second MOSFET in an OFF state in order to hold said second MOSFET in the high threshold voltage state;

wherein said first and second control transistors perform a complementary operation in accordance with the input signal.

9. A driver circuit according to claim 8,

wherein said first control transistor alternately applies the first and second voltages to said body terminal of said first MOSFET in accordance with the input signal applied to said gate terminal of said first MOSFET;

and

wherein said second control transistor alternately applies the first and third voltages to said body terminal of said second MOSFET in accordance with the input signal applied to said gate terminal of said second MOSFET.

10. A driver circuit according to claim 8,

wherein said first control transistor is constituted by a third MOSFET of the first conductivity type, and said first control transistor further comprises

a source connected to said body terminal of said first MOSFET,

a drain connected to said gate terminal of said first MOSFET, and

a gate to which a first gate voltage turning on said first control transistor, is applied;

and

wherein said second control transistor is constituted by a fourth MOSFET of the second conductivity type, and said second control transistor further comprises

a source connected to said body terminal of said second MOSFET,

a drain connected to said gate terminal of said second MOSFET, and

a gate to which a second gate voltage turning on said second control transistor, is applied.

11. A driver circuit comprising:

a first MOSFET of a first conductivity type;

a second MOSFET of a second conductivity type connected in series to said first MOSFET, said first and second MOSFETs each having a sate terminal configured to receive an input signal;

a first control transistor configured to apply a first voltage to a body terminal of said first MOSFET in an ON state in order to hold said first MOSFET in a low threshold voltage state, and configured to apply a second voltage to said body terminal of said first MOSFET in an OFF state in order to hold said first MOSFET in a high threshold voltage state; and

a second control transistor configured to apply the first voltage to a body terminal of said second MOSFET in an ON state in order to hold said second MOSFET in the low threshold voltage state, and configured to apply a third voltage to said body terminal of said second MOSFET in an OFF state in order to hold said second MOSFET in the high threshold voltage state;

wherein said first and second control transistors perform a complementary operation in accordance with the input signal;

wherein said first control transistor is constituted by a third MOSFET of the first conductivity type, and said first control transistor further comprises

a source connected to said body terminal of said first MOSFET,

a drain connected to a drain terminal of said first MOSFET, and

a gate connected to said gate terminal of said first MOSFET; and

wherein and said second control transistor is constituted by a fourth MOSFET of the second conductivity type, and said second control transistor further comprises

a source connected to said body terminal of said second MOSFET,

a drain connected to a drain terminal of said second MOSFET, and

a gate connected to said gate terminal of said second MOSFET.