High speed capture latch
First Claim
1. A latch comprising:
- a latch clock input;
a boost clock input;
first and second voltage supply terminals;
a current steering circuit having first and second differential control terminals which control current through first and second current paths;
a switched current source coupled between the current steering circuit and the first voltage supply terminal and having a control terminal coupled to the latch clock input;
a latch element coupled between the second voltage supply terminal and the current steering circuit and having a latch output;
a first boost current source coupled to the first current path between the latch element and the current steering circuit and having a control terminal coupled to the boost clock input; and
a second boost current source coupled to the second current path between the latch element and the current steering circuit and having a control terminal coupled to the boost clock input.
7 Assignments
0 Petitions
Accused Products
Abstract
A high speed capture latch includes differential data inputs, a latch clock input, a boost clock input, a current steering circuit, a switched current source, a latch element and first and second boost current sources. The current steering circuit has first and second differential control terminals which are coupled to the differential data inputs and control current through first and second current paths, respectively. The switched current source is coupled between the current steering circuit and a first voltage supply terminal and has a control terminal coupled to the latch clock input. The latch element is coupled between a second voltage supply terminal and the current steering circuit and provides a latch output. The first boost current source is coupled to the first current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input. The second boost current source is coupled to the second current path between the latch element and the current steering circuit and has a control terminal coupled to the boost clock input.
37 Citations
17 Claims
-
1. A latch comprising:
-
a latch clock input; a boost clock input; first and second voltage supply terminals; a current steering circuit having first and second differential control terminals which control current through first and second current paths; a switched current source coupled between the current steering circuit and the first voltage supply terminal and having a control terminal coupled to the latch clock input; a latch element coupled between the second voltage supply terminal and the current steering circuit and having a latch output; a first boost current source coupled to the first current path between the latch element and the current steering circuit and having a control terminal coupled to the boost clock input; and a second boost current source coupled to the second current path between the latch element and the current steering circuit and having a control terminal coupled to the boost clock input. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
-
-
15. A latch for sampling a data signal, comprising:
-
first and second data inputs for receiving the data signal; a latch clock input for receiving a latch clock signal; a boost clock input for receiving a boost clock signal; steering means coupled to the first and second data inputs for steering current through first and second current paths as a function of the data signal; current source means coupled to the steering means and to the latch clock input for supplying a current to the first and second current paths as a function of the latch clock signal; latch means coupled to the steering means for generating a latched data output as a function of the current through the first and second current paths; and boost current means coupled to the first and second current paths, between the latch means and the steering means, and coupled to the boost clock input for supplying a boost current to the first and second current paths as a function of the boost clock signal.
-
-
16. A precharged latch comprising:
-
first and second voltage supply terminals; a latch clock input for receiving a latch clock signal having first and second logic states; a boost clock input for receiving a boost clock signal having first and second logic states; a latch circuit coupled to the latch clock input and between the first and second voltage supply terminals, wherein the latch circuit comprises a latch input and first and second complementary latch outputs within first and second current paths, respectively, and wherein the latch circuit is active on the first logic state of the latch clock signal; a first precharge transistor having a first terminal coupled to the second voltage supply terminal, a second terminal coupled to the first complementary latch output, and a control terminal coupled to the latch clock input; a second precharge transistor having a first terminal coupled to the second voltage supply terminal, a second terminal coupled to the second complementary latch output, and a control terminal coupled to the latch clock input; wherein the first and second precharge transistors are active on the second logic states of the latch clock signal; a first boost current source coupled to the first current path and having a control terminal coupled to the boost clock input; a second boost current source coupled to the second current path and having a control terminal coupled to the boost clock input; and wherein the first and second boost current sources are active on only one of the first and second logic states of the boost clock signal. - View Dependent Claims (17)
-
Specification