Method and apparatus for providing high voltage with a low voltage CMOS integrated circuit
First Claim
1. A device for providing a high voltage to a node of a low voltage integrated circuit, the device comprising:
- a pull up circuit coupled between the high voltage and the node, the pull up circuit configured to pull the node up to approximately the high voltage; and
a pull down circuit coupled between the node and a second voltage, the pull down circuit configured to pull the node down to a third voltage, the pull down circuit including series coupled first and second n-channel transistors, the first n-channel transistor having a first substrate junction breakdown voltage, the second n-channel transistor having a second substrate junction breakdown voltage wherein the first substrate junction breakdown voltage is greater than the second substrate junction breakdown voltage.
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Accused Products
Abstract
A method and an apparatus for providing a high voltage to a node of a low voltage tolerant CMOS integrated circuit process. In one embodiment, a pull up circuit is coupled between a high voltage source and the node and a pull down circuit is coupled between the node and a second voltage. The pull up circuit is configured to pull the voltage at the node to a high voltage while the pull down circuit is configured to the voltage at the node to a lower voltage. The pull down circuit includes a pair of series coupled n-channel transistors coupled between the node and the second voltage. The n-channel transistor connected to the node is a special n-channel transistor with a drain to substrate junction breakdown that is greater than the drain to substrate junction breakdown voltage of other ordinary n-channel transistors in the process. The special n-channel transistor is manufactured in an ordinary state-of-the-art CMOS integrated circuit process without adding any costly process steps.
79 Citations
30 Claims
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1. A device for providing a high voltage to a node of a low voltage integrated circuit, the device comprising:
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a pull up circuit coupled between the high voltage and the node, the pull up circuit configured to pull the node up to approximately the high voltage; and a pull down circuit coupled between the node and a second voltage, the pull down circuit configured to pull the node down to a third voltage, the pull down circuit including series coupled first and second n-channel transistors, the first n-channel transistor having a first substrate junction breakdown voltage, the second n-channel transistor having a second substrate junction breakdown voltage wherein the first substrate junction breakdown voltage is greater than the second substrate junction breakdown voltage. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A device for providing a high voltage to a node of a low voltage integrated circuit comprising:
a differential cascode voltage switch having first and second paths coupled between the high voltage and a first voltage, the first path having a first output node and the second path having a second output node wherein first and second n-channel transistors are coupled between the first output node and the first voltage and third and fourth n-channel transistors are coupled between the second output node and the first voltage, wherein the first and third n-channel transistors have a first substrate junction breakdown voltage and the second and fourth n-channel transistors have a second substrate junction breakdown voltage, wherein the first substrate junction breakdown voltage is greater than the second substrate junction breakdown voltage. - View Dependent Claims (8, 20)
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9. A device for programming and sensing an antifuse circuit, the device comprising:
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a programming circuit coupled to the antifuse circuit, the programming circuit configured to program the antifuse circuit, the programming circuit including series coupled first and second n-channel transistors, the first n-channel transistor having a first substrate junction breakdown voltage, the second n-channel transistor having a second substrate junction breakdown voltage wherein the first substrate junction breakdown voltage is greater than the second substrate junction breakdown voltage; and a sensing circuit coupled to the antifuse circuit, the sensing circuit configured so as to generate a sense output signal in response to a condition of the antifuse circuit. - View Dependent Claims (10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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21. A device for programming and sensing an antifuse circuit, the device comprising:
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a programming circuit coupled to the antifuse circuit, the programming circuit configured to program the antifuse circuit, the programming circuit configured to alter a condition of the antifuse circuit in response to a write enable signal; and a sensing circuit coupled to the antifuse circuit, the sensing circuit configured to generate a sense output signal in response to a condition of the antifuse circuit, the sensing circuit including a current mirror circuit having first and second paths coupled between first and second voltages, the first path including series coupled first p-channel and first n-channel transistors and the antifuse circuit, the second path including series coupled second p-channel and second n-channel transistors, the first n-channel transistor having a first substrate junction breakdown voltage, the second n-channel transistor having a second substrate junction breakdown voltage wherein the first substrate junction breakdown voltage is greater than the second substrate junction breakdown voltage. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A method for providing a high voltage at a node of a low voltage CMOS integrated circuit comprising the steps of:
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pulling a voltage at the node up to the high voltage with a pull up circuit in response to a first control signal; pulling the voltage at the node down to a lower voltage with a pull down circuit in response to a second control signal, the pull down circuit including a high voltage device coupled to a regular device; protecting the pull down circuit from junction breakdown with the high voltage device wherein the high voltage device has a first substrate junction breakdown voltage and the regular device has a second substrate junction breakdown voltage, wherein the first substrate junction breakdown voltage is greater than the second substrate junction breakdown voltage. - View Dependent Claims (28, 29, 30)
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Specification