Method and apparatus for converting an analog signal into digital format

• US 5,748,134 A
• Filed: 03/01/1996
• Issued: 05/05/1998
• Est. Priority Date: 03/01/1996
• Status: Expired due to Term

• Current Assignee: Unwired Planet LLC (JP Morgan Chase & Co)
• Original Assignee: Ericsson, Inc. (Telefonaktiebolaget LM Ericsson)
• Inventors: Dent, Paul Wilkinson
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/609,715
• Time in Patent Office: 795 Days
• Field of Search: 341/157, 341/164, 341/172
• US Class Current: 341/172
• CPC Class Codes: H03M 1/54 Input signal sampled and held with linear return to datum

Abstract

A low cost, easily manufactured analog to digital converter uses MOS switching technology easily combined on an integrated circuit with other signal processing circuitry. An input capacitor stores an input analog voltage, and a pumping capacitor is switchably connected to the input capacitor to charge or discharge that input capacitor to a reference value. The number of charge or discharge events is used to generate a digital value for the input analog voltage.

Claims

1. An analog to digital converter, comprising:

a first capacitor connected at a first terminal to an analog signal to charge the capacitor in accordance with a current voltage level of the analog signal and at a second terminal to ground;

a second capacitor; and

electronic control circuitry for alternately connecting the second capacitor between the first capacitor and a power supply to remove increments of charge from the first capacitor until the first capacitor is discharged including;

a switching circuit connected to the first terminal of the first capacitor, to ground, and to the power supply including;

a first pair of switches with one switch connected to a first terminal of the second capacitor and the other switch connected to a second terminal of the second capacitor, and

a second pair of switches with one switch connected to a first terminal of the second capacitor and the other switch connected to a second terminal of the second capacitor,

wherein the electronic control circuitry generates switching control signals alternately connecting the second capacitor through the first pair of switches between ground and the power supply and through the second pair of switches between the first terminal of the first capacitor and ground to remove the increments of charge from the first capacitor, and

wherein a number of removed increments of charge associated with discharging the first capacitor is used to generate a digital value corresponding to the current voltage level of the analog signal.

2. The analog to digital converter in claim 1, further comprising:

a multiplexer for receiving multiple analog signals and selecting one of the received analog signals for connection to the first capacitor in response to a control signal received from the electronic control circuitry,

wherein after the first capacitor charges to a level commensurate with the current voltage level of the selected analog signal, the electronic control circuitry causes the multiplexer to disconnect the analog signal from the first capacitor.

3. The analog to digital converter in claim 1, further comprising:

a comparator having one input connected to the first terminal of the first capacitor and another input connected to ground for detecting when the voltage across the first capacitor is at or nearly zero and then generating a detection signal causing the electronic control circuitry to generate the digital value.

4. The analog to digital converter in claim 2, further comprising a clock source, wherein the electronic control circuitry includes a counter for counting clock pulses generated by the clock source from a predetermined starting point after the first capacitor is charged until the detection signal is received from the comparator halts the counting, with the digital readout from the counter corresponding to the digital value.

5. The analog to digital converter in claim 1, wherein each switch in the first and second pairs of switches is a complementary semiconductor switch having an N-type, insulated gate, field effect transistor (FET) and a P-type, insulated gate, field effect transistor (FET).

6. The analog to digital converter in claim 1, further comprising:

a clock source for generating clock signals,

the electronic control circuitry including a counter for counting the clock signals and generating a counter output signal that alternates between a first state and a second state,

wherein the switching control signals include the counter output signal such that the first pair of switches is selected to connect the second capacitor between ground and the power supply when the counter output is in the first state and the second pair of switches is selected to connect the second capacitor between the first terminal of the first capacitor and ground.

7. An analog to digital converter comprising:

an input capacitor connected at a first terminal to store an analog voltage and at a second terminal to ground;

control circuitry connected to the input capacitor at the first terminal;

dynamic detection circuitry connected to the first terminal of the input capacitor for determining whether an input signal applied to a first input terminal of a comparator generated in response to the voltage across the input capacitor is equal to or greater than a nonzero, threshold voltage applied to a second input terminal of the comparator and for providing an output signal from the comparator to the control circuit indicating whether the input capacitor is discharged,

wherein said dynamic detection circuitry is connected through a pump capacitor to a pump output signal of the control circuitry, the control circuitry alternately charging and discharging the pump capacitor using the pump output signal and discharging the input capacitor by an increment of charge after each charge and discharge cycle of the pump capacitor, until the dynamic detection circuitry indicates that the input capacitor is discharged, a total number of incremental discharges of the input capacitor being used to generate a digital value for the analog voltage.

8. The analog to digital converter in claim 7, wherein the control circuit includes a counter for counting the number of incremental discharges to provide a digital code corresponding to a final count value.

9. The analog to digital converter in claim 7, further comprising:

a multiplexer for receiving multiple analog signals and selecting one of the received analog signals for connection to the input capacitor in response to a control signal received from the control circuit,

wherein after the input capacitor charges to a level commensurate with the current voltage level of the selected analog signal, the control circuit causes the multiplexer to disconnect the analog signal from the input capacitor.

10. The analog to digital converter in claim 7, further comprising:

a resistor connected in series with the pump capacitor between the control circuit and the dynamic detector.

11. The analog to digital converter in claim 7, wherein the dynamic detection circuitry includes a first field effect transistor (FET) having a gate electrode connected to ground and a second field effect transistor (FET) having a gate electrode connected to the first terminal of the first capacitor with drain electrodes being connected to a power supply,

the first and second FETs having a common source electrode connected to the pump capacitor, and

a drain electrode of the second FET connected to the first input terminal of the comparator.

12. The analog to digital converter in claim 11, wherein when the pump signal is in a first logic state, current flows in a first direction from either or both of the first and second FETs from the common source electrodes through the pump capacitor discharging the pump capacitor, and wherein the comparator compares a voltage at the first input terminal with the nonzero, threshold voltage during a comparison time interval when the pump signal is in the first logic state.

13. The analog to digital converter in claim 12, wherein the common source is connected by a diode to ground such that when the pump signal is in a second logic state, current flows in a second direction opposite the first direction through the diode to charge up the pump capacitor, and wherein during a discharge time interval when the pump signal is in the second logic state, the control circuit discharges the input capacitor by an increment discharge if the comparator indicates during an immediately preceding comparison time interval that the input capacitor is not discharged.

14. The analog to digital converter in claim 11, wherein the dynamic detection circuitry further includes a current mirror circuit connected between the drain electrodes of the first and second FETs and the power supply.

15. The analog to digital converter in claim 14, wherein the current mirror includes a third FET connected at its source electrode to a voltage supply and at its drain electrode to the second FET and to the first input terminal of the comparator and a fourth FET connected at its source electrode to the power supply, at its drain electrode to the drain electrode to the drain electrode of the first FET, and at its gate electrode to the a gate electrode of the third FET and to the drain electrode of the fourth FET.

16. The analog to digital converter in claim 11, wherein the first and second transistors are formed in a well of a first conductivity type diffused into a substrate of a second conductivity type.

17. An analog to digital converter, comprising:

a first capacitor connected at a first terminal to an analog signal to charge the capacitor in accordance with a current voltage level of the analog signal and at a second terminal to ground;

a comparator having one input terminal connected to the first terminal of the first capacitor and another input terminal connected to a reference voltage for generating;

(a) a first signal when the voltage across the first capacitor is greater than the reference voltage,

(b) a second signal when the voltage across the first capacitor is less than the reference voltage, and

(c) a third signal when the voltage across the first capacitor is the same as the reference voltage; and

electronic control circuitry for supplying increments of charge to the first capacitor when the second signal is generated until the third signal is generated and for removing increments of charge from the first capacitor when the first signal is generated until the third signal is generated,

wherein the electronic control circuitry counts a number of charge increments or decrements to generate a digital value corresponding to the current voltage level of the analog signal.

18. The analog to digital converter in claim 17, further comprising:

a second capacitor for storing the increment of charge, and

a plurality of switches connected to the second capacitor,

wherein the electronic control circuitry alternately switches the second capacitor between various states depending on the output from the comparator.

19. The analog to digital converter in claim 17, wherein when the comparator generates the first signal, the electronic control circuitry generates control signals to successively activate switches to connect the second capacitor between a power supply and ground and then to connect the second capacitor to the first capacitor thereby removing increments of charge from the first capacitor until the third signal generated.

20. The analog to digital converter in claim 19, wherein each switch is an insulated gate, field effect transistor (FET).

21. The analog to digital converter in claim 17, wherein when the comparator generates the second signal, the control circuitry generates control signals to activate switches to successively connect the second capacitor between a power supply and ground and then to connect the second capacitor to the first capacitor to add increments of charge from the first capacitor until the third signal generated.

22. The analog to digital converter in claim 21, wherein each switch is an insulated gate, field effect transistor (FET).

23. The analog to digital converter in claim 17, wherein the reference voltage is a nonzero voltage.

24. The analog to digital converter in claim 17, further comprising:

a multiplexer for receiving multiple analog signals and selecting one of the received analog signals for connection to the first capacitor in response to a control signal received from the electronic control circuitry,

wherein after the first capacitor charges to a level commensurate with the current voltage level of the selected analog signal, the electronic control circuitry causes the multiplexer to disconnect the analog signal from the first capacitor.

25. A method for converting an analog signal into a digital signal comprising the steps of:

charging a first capacitor in accordance with a current voltage level of the analog signal;

comparing the voltage across the first capacitor to a reference voltage;

supplying increments of charge to the first capacitor when a voltage across the capacitor is less than a reference voltage and removing increments of charge when the voltage across the first capacitor is greater than the reference voltage; and

counting a number of the charge increments or decrements to generate a digital value corresponding to the current voltage level of the analog signal.

26. The method in claim 25, wherein the increments of charge are supplied until the charge across the first capacitor is the same as the reference voltage.

27. The method in claims 25, wherein the increments of charge are removed until the charge across the first capacitor is the same as the reference voltage.

28. The method in claim 25, further comprising the step of:

discontinuing supplying increments of charge when the first capacitor is discharged and then performing the counting step.