Computer system architecture that incorporates display memory into system memory

• US 5,748,203 A
• Filed: 03/04/1996
• Issued: 05/05/1998
• Est. Priority Date: 03/04/1996
• Status: Expired due to Term

• Current Assignee: United Microelectronics Corporation
• Original Assignee: United Microelectronics Corporation
• Inventors: Yen, Chih-Chan, Tang, Tsan-Bih
• Primary Examiner(s): Kim, Matthew M.
• Assistant Examiner(s): CHAUHAN, ULKA J
• Application Number:
  US08/610,456
• Time in Patent Office: 792 Days
• Field of Search: 395/501, 395/503, 395/507, 395/511, 395/512, 395/515, 395/518, 395/520, 395/521, 395/432, 395/433, 395/474, 395/480, 365/189.01, 365/189.05, 345/501, 345/503, 345/507, 345/511, 345/512, 345/515, 345/518, 345/520, 345/521, 345/432, 345/433, 711/105, 711/106, 711/147, 711/151
• US Class Current: 345/542
• CPC Class Codes: G06F 13/1605 based on arbitration arbitration in handling access to a common bus or bus system G06F13/36
• CPC Class Codes: G06F 3/14 Digital output to display device ; Cooperation and interconnection of the display device with other functional units
• CPC Class Codes: G09G 2360/125 using unified memory architecture [UMA]
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory

Abstract

A computer architecture that incorporates display memory into system memory is disclosed, which comprises a memory, a memory controller and a display controller. Both of the memory controller and the display controller are employed to control access of the memory device having system data and display data stored therein. Built-in signals and an arbiter are provided between the controllers to arbitrate the priorities of the two controllers to access the memory device. Furthermore, request and grant signals are used to initiate the refresh of the main memory to maintain data therein. The control circuits of the two controllers to the memory device are connected to each other to prevent signals contention.

Claims

1. A computer architecture incorporating display memory into system memory, comprising:

a memory for storing both system data and display data;

a memory controller, connected to the memory, for controlling access of the system data; and

a display controller, connected to the memory, for controlling access of the display data, wherein the display controller includes means for providing to the memory controller a request signal requesting use of the memory, and the memory controller includes means for providing to the display controller a grant signal granting use of the memory to the display controller for arbitrating control of the memory by the display controller and the memory controller;

means for refreshing the memory, the refreshing means including means for generating a request signal by the display controller for causing a refresh operation; and

including means for carrying out a refresh operation after a data access request from the display controller and before a grant is received by the display controller.