Apparatus and method of orienting asymmetrical semiconductor devices in a circuit
First Claim
1. A computer implemented method of orienting asymmetrical semiconductor devices in an integrated circuit, comprising the steps of:
- providing first and second operating potentials where said first operating potential is more positive than said second operating potential;
combining a first type of asymmetrical semiconductor device between said first operating potential and a common node into a first combination block that includes only the first type of asymmetrical semiconductor device;
combining a second type of asymmetrical semiconductor device between said common node and said second operating potential into a second combination block that includes only the second type of asymmetrical semiconductor device;
coupling a source terminal of one of said first type of asymmetrical semiconductor device to a first node operating at a first potential and coupling a drain terminal of said one of said first type of asymmetrical semiconductor device to a second node operating at a second potential less than said first potential in said first combination block; and
coupling a source terminal of one of said second type of asymmetrical semiconductor device to a third node operating at a third potential and coupling a drain terminal of said one of said second type of asymmetrical semiconductor device to a fourth node operating at a fourth potential greater than said third potential in said second combination block.
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Accused Products
Abstract
A computer implemented method provides for orientation and lay-out asymmetrical semiconductor devices. The sources of operating potential (20, 30) are identified. The PMOS transistors (22-28) are combined between the first (more positive) source of operating potential and a common node (12) into a combination block (48). The NMOS transistors (14-18) are combined between the common node and the second (less positive) source of operating potential into another combination block (52). The PMOS source terminals are coupled to more positive potentials, and the PMOS drain terminals are coupled to less positive potentials within the first combination block. The NMOS source terminals are coupled to less positive potentials, and the NMOS drain terminals are coupled to more positive potentials within the second combination block. For transmission gates (60, 62), a driving source is identified and the PMOS and NMOS source terminals are coupled to the driving source.
8 Citations
14 Claims
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1. A computer implemented method of orienting asymmetrical semiconductor devices in an integrated circuit, comprising the steps of:
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providing first and second operating potentials where said first operating potential is more positive than said second operating potential; combining a first type of asymmetrical semiconductor device between said first operating potential and a common node into a first combination block that includes only the first type of asymmetrical semiconductor device; combining a second type of asymmetrical semiconductor device between said common node and said second operating potential into a second combination block that includes only the second type of asymmetrical semiconductor device; coupling a source terminal of one of said first type of asymmetrical semiconductor device to a first node operating at a first potential and coupling a drain terminal of said one of said first type of asymmetrical semiconductor device to a second node operating at a second potential less than said first potential in said first combination block; and coupling a source terminal of one of said second type of asymmetrical semiconductor device to a third node operating at a third potential and coupling a drain terminal of said one of said second type of asymmetrical semiconductor device to a fourth node operating at a fourth potential greater than said third potential in said second combination block. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An apparatus for orienting an asymmetrical semiconductor device in an integrated circuit, comprising:
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means for providing first and second operating potentials where said first operating potential is more positive than said second operating potential; means for combining a first type of asymmetrical semiconductor device between said first operating potential and a common node into a first combination block that includes only the first type of asymmetrical semiconductor device; means for combining a second type of asymmetrical semiconductor device between said common node and said second operating potential into a second combination block that includes only the second type of asymmetrical semiconductor device; means for coupling a source terminal of one of said first type of asymmetrical semiconductor device to a first node operating at a first potential and coupling a drain terminal of said one of said first type of asymmetrical semiconductor device to a second node operating at a second potential less than said first potential in said first combination block; and means for a coupling source terminal of one of said second type of asymmetrical semiconductor device to a third node operating at a third potential and coupling a drain terminal of said one of said second type of asymmetrical semiconductor device to a fourth node operating at a fourth potential greater than said third potential in said second combination block. - View Dependent Claims (8, 9, 10)
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11. An asymmetrical semiconductor device oriented by the steps comprising:
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providing first and second operating potentials where said first operating potential is more positive than said second operating potential; combining a first type of asymmetrical semiconductor device between said first operating potential and a common node into a first combination block that includes only the first type of asymmetrical semiconductor device; combining a second type of asymmetrical semiconductor device between said common node and said second operating potential into a second combination block that includes only the second type of asymmetrical semiconductor device; coupling a source terminal of one of said first type of asymmetrical semiconductor device to a first node operating at a first potential and coupling a drain terminal of said one of said first type of asymmetrical semiconductor device to a second node operating at a second potential less than said first potential in said first combination block; and coupling a source terminal of one of said second type of asymmetrical semiconductor device to a third node operating at a third potential and coupling a drain terminal of said one of said second type of asymmetrical semiconductor device to a fourth node operating at a fourth potential greater than said third potential in said second combination block. - View Dependent Claims (12, 13, 14)
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Specification