System and method for improving fault coverage of an electric circuit

• US 5,748,497 A
• Filed: 10/31/1994
• Issued: 05/05/1998
• Est. Priority Date: 10/31/1994
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Scott, Kyl W., Skidmore, James M.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): VO, HIEN XUAN
• Application Number:
  US08/332,237
• Time in Patent Office: 1,282 Days
• Field of Search: 364/580, 364/551.01, 371/22.1, 371/22.6, 371/25.1, 371/27, 395/183.01, 395/183.06, 395/183.11
• US Class Current: 702/181
• CPC Class Codes: G01R 31/31835 Analysis of test coverage or failure detectability
• CPC Class Codes: G01R 31/318378 of patterns for devices arranged in a network

Abstract

The present invention is a method and system which determine signal probability and transfer probability for each node in a netlist describing an electrical circuit; determine, using the signal probability and transfer probability, a fault detection probability for each node; and, using the fault detection probabilities, determine overall fault coverage of the electrical circuit described in the netlist. The method and system of the present invention then, using the fault coverage data, heuristically determine a set of testpoints to be inserted into the netlist which increase the overall fault coverage of the electrical circuit above a predetermined value.

Claims

1. A computer implemented method for selecting testpoints to increase overall fault coverage of an electrical circuit, said computer including a memory and a display, comprising the steps of:

providing a netlist of a plurality of circuit design cells describing said electrical circuit in said memory of said computer, said netlist identifying a plurality of nodes and a plurality of connections between said plurality of nodes;

generating a scan path through said plurality of circuit design cells and said plurality of nodes in said netlist in response to a user request comprising the steps of ordering said plurality of circuit design cells to be scanned and inserting dummy scan cells into said scan path to eliminate register adjacency;

determining a fault grade associated with each of said plurality of nodes included in said scan path through said netlist;

measuring potential effectiveness of insertion of a testpoint at each of said plurality of nodes in response to said determining step;

selecting a first set of testpoints that enhance controllability of said electrical circuit described in said netlist in response to said measuring step;

selecting a second set of testpoints that enhance observability of said electrical circuit described in said netlist in response to said measuring step;

ranking said first set of testpoints and said second set of testpoints in accordance with said potential effectiveness thereby generating a third set of testpoints, each of said testpoints having an associated rank; and

repeatedly inserting one of said testpoints included in said third set of testpoints into said netlist in accordance with said associated rank until a desired fault coverage for said electrical circuit described in said netlist is obtained, thereby generating an updated netlist.

2. The method of claim 1 further including the step of generating a simulation of said electrical circuit described in said updated netlist and displaying said simulation on a display of said computer.

3. The method of claim 1 wherein said determining step includes the step of determining said fault grade using a stuck-at-0/1 logic gate fault model.

4. The method of claim 1 wherein said determining step includes the steps of:

calculating a signal probability associated with each of said plurality of nodes in said netlist;

calculating a transfer probability associated with each of said plurality of nodes in said netlist;

calculating a fault detection probability associated with each of said plurality of nodes in response to said steps of calculating said signal probability and said transfer probability; and

calculating a fault coverage probability associated with each of said plurality of nodes in said netlist in response to said step of calculating said fault detection probability.

5. The method of claim 1 wherein said repeatedly inserting step includes the step of repeatedly inserting an optimum configuration of one of said testpoints included in said third set of testpoints into said netlist in accordance with an associated rank until a minimum fault detection coverage for said electrical circuit described in said netlist is attained.