Semiconductor nonvolatile memory device and computer system using the same

• US 5,748,532 A
• Filed: 07/10/1996
• Issued: 05/05/1998
• Est. Priority Date: 07/10/1995
• Status: Expired due to Term

• Current Assignee: PS4 Luxco S.a.r.l.
• Original Assignee: Hitachi, Ltd.
• Inventors: Miyazawa, Kazuyuki, Tanaka, Toshihiro, Oshima, Kazuyoshi, Kato, Masataka, Kimura, Katsutaka, Tsujikawa, Tetsuya
• Primary Examiner(s): Popek, Joseph A.
• Application Number:
  US08/677,842
• Time in Patent Office: 664 Days
• Field of Search: 365/185.22, 365/185.24, 365/185.18, 365/185.27, 365/185.28
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 7/103 using serially addressed read-write data registers G11C7/1036 takes precedence

Abstract

A semiconductor nonvolatile memory device including transistors whose threshold voltages can be electrically rewritten (erased, written). A read-selected word line voltage Vrw, lower than the supply voltage Vcc applied from the outside, is applied, and the threshold voltage difference between the higher threshold voltage VthH and the lower threshold voltage VthL in the two states of the nonvolatile memory cells is reduced to bring the higher threshold voltage VthH close to the lower threshold voltage VthL. Moreover, a threshold voltage Vthi in the thermally equilibrium state of the memory cell, corresponding to the two threshold voltages of the two states, is set between the higher threshold voltage VthH and the lower threshold voltage VthL.

Claims

1. A semiconductor nonvolatile memory device comprising:

a plurality of word lines;

a plurality of memory cells each of which has a control gate and a floating gate and which stores data as a threshold voltage;

an external data terminal to which data is applied; and

one external supply voltage terminal to which a positive supply voltage is applied,

wherein each of said plurality of memory cells is coupled to a corresponding word line of said plurality of word lines, and

wherein a read voltage to be applied to a selected word line in a read operation for outputting, through said external data terminal, data of memory cells coupled to said selected word line is higher than 0 V and is lower than said positive supply voltage applied to said one external supply voltage terminal.

2. A semiconductor nonvolatile memory device according to claim 1, wherein said read voltage is produced by lowering said positive supply voltage.

3. A semiconductor nonvolatile memory device according to claim 2, wherein said read voltage is at ±

0.5 V of the threshold voltage in a thermally equilibrium state of said plurality of memory cells.

4. A semiconductor nonvolatile memory device according to claim 3, wherein the threshold voltage in the thermally equilibrium state of said memory cell is defined to be between the individual threshold voltages corresponding to binary information.

5. A semiconductor nonvolatile memory device according to claim 4, wherein said individual threshold voltages corresponding to said binary information have substantially equal potential differences from the threshold voltage in the thermally equilibrium state of said memory cell.

6. A semiconductor nonvolatile memory device according to claim 5, wherein said potential differences are at 0.5 to 2.0 V.

7. A semiconductor nonvolatile memory device according to claim 6, wherein a serial access can be made to selected memory cells of said plurality of memory cells.

8. A semiconductor nonvolatile memory device according to claim 7, wherein the data are read out by serially accessing selected memory cells of said plurality of memory cells.

9. A semiconductor nonvolatile memory device according to claim 8, wherein said positive supply voltage is +3.3 V.

10. A computer system comprising:

a semiconductor nonvolatile memory device; and

a central processing unit coupled to be in electrical communication with the nonvolatile memory device

wherein said semiconductor nonvolatile memory device, includes;

a plurality of word lines;

a plurality of memory cells each of which has a control gate and a floating gate and which stores data as a threshold voltage;

an external data terminal to which data is applied; and

one external supply voltage terminal to which a positive supply voltage is applied,

wherein each of said plurality of memory cells is coupled to a corresponding word line of said plurality of word lines, and

wherein a read voltage to be applied to a selected word line in a read operation for outputting, through said external data terminal, data of memory cells coupled to said selected word line is higher than 0 V and is lower than said positive supply voltage applied to said one external supply voltage terminal.

11. A semiconductor nonvolatile memory device according to claim 11, wherein said positive supply voltage is +3.3 V.

12. A semiconductor nonvolatile memory device which comprises:

one external voltage terminal to which a positive supply voltage is applied;

a memory cell array including a plurality of nonvolatile semiconductor memory cells each having a control gate, a floating gate, a drain and a source, and arranged in an array;

a plurality of word lines to each of which the control gates of corresponding memory cells of said plurality of memory cells are commonly coupled;

a plurality of data lines to each of which the drains of corresponding memory cells of said plurality of memory cells are commonly coupled; and

sense latch circuits each of which is coupled to a corresponding data line of said plurality of data lines wherein in a read operation, in which said sense latch circuits store data of memory cells coupled to a selected word line, a read voltage which is applied to said selected word line from said plurality of word lines is lower than said positive supply voltage and is higher than 0 V.

13. A semiconductor nonvolatile memory device according to claim 12, wherein said read voltage is produced by lowering said positive supply voltage.

14. A semiconductor nonvolatile memory device according to claim 13, wherein said read voltage is at ±

0.5 V of the threshold voltage in a thermally equilibrium state of said plurality of memory cells.

15. A semiconductor nonvolatile memory device according to claim 14, wherein the threshold voltage in the thermally equilibrium state of said memory cell is defined to be between the individual threshold voltages corresponding to binary information.

16. A semiconductor nonvolatile memory device according to claim 15, wherein said individual threshold voltages corresponding to said binary information have substantially equal potential differences from the threshold voltage in the thermally equilibrium state of said memory cell.

17. A semiconductor nonvolatile memory device according to claim 16, wherein said potential differences are at 0.5 to 2.0 V.

18. A semiconductor nonvolatile memory device according to claim 17, wherein a serial access can be made to selected memory cells of said plurality of memory cells.

19. A semiconductor nonvolatile memory device according to claim 18, wherein the data are read out by serially accessing selected memory cells of said plurality of memory cells.

20. A semiconductor nonvolatile memory device according to claim 19, further comprising a data terminal which is supplied with data, said data terminal being coupled to said data lines via said sense latch circuits, respectively.

21. A semiconductor nonvolatile memory device according to claim 20, wherein said data which is stored in said sense latch circuits, in said read operation, is sequentially supplied to said data terminal.

22. A semiconductor nonvolatile memory device according to claim 21, wherein said positive supply voltage is +3.3 V.

23. A computer system comprising:

a semiconductor nonvolatile memory device; and

a central processing unit, coupled to be in electrical communication with the nonvolatile memory device,

wherein said semiconductor nonvolatile memory device includes;

one external supply voltage terminal to which a positive supply voltage is applied,

a memory cell array including a plurality of nonvolatile semiconductor memory cells each having a control gate, a floating gate, a drain and a source, and arranged in an array;

a plurality of word lines to each of which the control gates of corresponding memory cells of said plurality of memory cells are commonly coupled;

a plurality of data lines to each of which the drains of corresponding memory cells of said plurality of memory cells are commonly coupled; and

sense latch circuits each of which is coupled to a corresponding data line of said plurality of data lines,

wherein in a read operation, in which said sense latch circuits store data of memory cells coupled to a selected word line, a read voltage which is applied to said selected word line is lower than said positive supply voltage and is higher than 0 V.

24. A semiconductor nonvolatile memory device according to claim 23, wherein said positive supply voltage is +3.3 V.

25. A semiconductor nonvolatile memory device which comprises:

one external voltage terminal to which a positive supply voltage is applied;

a memory cell array including a plurality of nonvolatile semiconductor memory cells each having a control gate, a floating gate, a drain and a source, and arranged in an array;

a plurality of word lines to each of which the control gates of corresponding memory cells of said plurality of memory cells are commonly coupled;

a plurality of data lines to each of which the drains of corresponding memory cells of said plurality of memory cells are commonly coupled; and

sense latch circuits each of which includes a flip-flop circuit coupled to said one external voltage terminal and each of which is coupled to a corresponding data line of said plurality of data lines,

wherein in a read operation, in which said sense latch circuits store data of memory cells coupled to a selected word line, a read voltage which is applied to said selected word line from said plurality of word lines is lower than said positive supply voltage and is higher than 0 V.

26. A semiconductor nonvolatile memory device according to claim 25, wherein said read voltage is produced by lowering said positive supply voltage.

27. A semiconductor nonvolatile memory device according to claim 26, wherein threshold voltages of said plurality of memory cells are in one of a first region lower than said read voltage and a second region higher than said read voltage, a threshold voltage in said thermally equilibrium state is defined to be between said first region and said second region.

28. A semiconductor nonvolatile memory device according to claim 27, wherein said read voltage is at ±

0.5 V of the threshold voltage in a thermally equilibrium state of said plurality of memory cells.

29. A semiconductor nonvolatile memory device according to claim 28, wherein a potential difference between said first region and said threshold voltage in said thermally equilibrium state is substantially equal to a potential difference between said second region and said threshold voltage in said thermally equilibrium state.

30. A semiconductor nonvolatile memory device according to claim 29, wherein said potential differences are 0.5 to 2.0 V.

31. A semiconductor nonvolatile memory device according to claim 30, wherein a serial access can be made to selected memory cells of said plurality of memory cells.

32. A semiconductor nonvolatile memory device according to claim 31, wherein said data which is stored in said sense latch circuits, in said read operation, is sequentially supplied to said data terminal.

33. A semiconductor nonvolatile memory device according to claim 32, wherein said read voltage is at ±

0.5 V of the threshold voltage in a thermally equilibrium state of said plurality of memory cells.