Read circuit which uses a coarse-to-fine search when reading the threshold voltage of a memory cell

• US 5,748,533 A
• Filed: 03/26/1996
• Issued: 05/05/1998
• Est. Priority Date: 03/26/1996
• Status: Expired due to Term

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Invoice Technology Incorporated
• Inventors: Dunlap, Frank M, So, Hock C., Wong, Sau C.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NIRANJAN, FRANK
• Application Number:
  US08/622,332
• Time in Patent Office: 770 Days
• Field of Search: 365/185.19, 365/185.01, 365/185.03, 365/185.23, 365/230.06, 365/185.18
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5621 using charge storage in a floating gate
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 27/005 with non-volatile charge storage, e.g. on floating gate or MNOS
• CPC Class Codes: G11C 7/16 Storage of analogue signals in digital stores using an arrangement comprising analogue/digital [A/D] converters, digital memories and digital/analogue [D/A] converters

Abstract

A read circuit includes a driver which changes a gate voltage of a memory cell and a sense circuit which identifies when the memory cell trips. The driver searches for the threshold voltage of the memory cell using stages which ramp up gate voltage and stages which ramp down the gate voltage. Each stage ends when the sense circuit senses that the memory cell trips, i.e. begins or stops conducting. Initial stages of the search have high ramp rates so that the gate voltage reaches the threshold voltage. These initial stages can give inaccurate threshold voltage readings because high ramp rates change the gate voltage during the period between the transistor tripping and sensing the trip. Later stages ramp the gate voltage slowly to provide an accurate threshold voltage reading. The low ramp rate of the last stage provides accuracy, and the high ramp rate of the initial stages reduces read time. To further reduce read time, the search process can begin at a median voltage for possible threshold voltages.

Claims

1. A read circuit comprising:

a driver which is operable in a first mode to ramp up an output voltage which is applied to a gate in a selected memory cell during a read process and operable in a second mode to ramp down the output voltage which is applied to the gate in the selected memory cell during the read process;

a sense circuit which generates a first signal indicating whether the selected memory cell conducts a first current; and

a control circuit coupled to the sense circuit and the driver, wherein during the read process, the control circuit switches the driver between the first mode and second mode in response to changes in the first signal from the sense circuit.

2. The read circuit of claim 1, further comprising a sample-and-hold circuit coupled to sample the output voltage of the driver, wherein a sample taken by the sample-and-hold circuit indicates a value read by the read circuit.

3. The read circuit of claim 1, wherein:

the driver comprises circuitry for ramping the output voltage at different rates; and

the control circuit comprises circuitry for selecting that the driver ramp the output voltage at a first rate during a stage in a read process and ramp the output voltage at a second rate at an end of the read process, the second rate being lower than the first rate.

4. The read circuit of claim 3, further comprising a sample-and-hold circuit coupled to sample the output voltage of the driver at the end of the read process, wherein a sample taken by the sample-and-hold circuit indicates a value read by the read circuit.

5. The read circuit of claim 1, wherein the driver comprises:

a first plurality of loads coupled to a voltage source;

a second plurality of loads coupled to ground;

a capacitor coupled to an output terminal which provides the output voltage; and

selection circuitry which connects selected loads from the first and second pluralities to the output terminal, wherein a rate and direction of ramping of the output voltage depends on which loads are connected to the output terminal.

6. The read circuit of claim 1, further comprising a row decoder coupled between the driver and an array of memory cells, and a column decoder coupled between the sense circuitry and the array.

7. The read circuit of claim 1, wherein the sense circuit comprises:

a reference cell which is structurally identical to the selected memory cell;

a first bias circuit which biases the reference cell to conduct a reference current, the first bias circuit containing a first node;

a second bias circuit which biases a source and a drain in the selected memory cell so that when the selected memory cell conducts the first current, a voltage on a second node in the second bias circuit is equal to a voltage on the first node in the first bias circuit; and

a differential amplifier having a first input terminal coupled to the first node and a second input terminal coupled to the second node, wherein the differential amplifier generates the first signal.

8. The read circuit of claim 7, wherein:

the first bias circuit comprises a first transistor coupled between a supply voltage and a current carrying terminal of the reference cell; and

the second bias circuit comprises a second transistor coupled between the supply voltage and a current carrying terminal of the selected memory cell, wherein

a gate and drain of the first transistor are coupled to each other and to a gate of the second transistor to form a current mirror.

9. The read circuit of claim 8, wherein:

the first bias circuit further comprises a reference voltage generator which applies a reference voltage to a gate of the reference cell;

the first transistor is structurally identical to the second transistor; and

the first current is equal to the reference current.

10. The read circuit of claim 8, wherein:

the output voltage of the driver is applied to a gate of the reference cell;

the reference cell has a threshold voltage that is at least as low as a lowest possible threshold voltage for the selected cell;

the first transistor is larger than the second transistor; and

the first current is smaller that the reference current.

11. A memory comprising:

an array of memory cells which includes word lines and bit lines, each word line being coupled to control gates of a row of memory cells in the array, each bit line being coupled to a column of memory cells in the array;

a driver which is operable in a first mode to ramp up a voltage on a selected word line during a read process and operable in a second mode to ramp down the voltage on the selected word line during the read process;

a sense circuit which generates a sense signal indicating whether a selected bit line conducts a first current; and

a control circuit coupled to the sense circuit and the driver, wherein during the read process, the control circuit switches the driver between the first mode and second mode in response to changes in the sense signal.

12. The memory of claim 11, wherein:

the driver comprises circuitry for ramping the voltage on the selected word line, at different rates; and

the control circuit comprises circuitry for selecting that the driver ramp the output voltage at a first rate during a stage of the read process and ramp the output voltage at a second rate at an end of the read process, the second rate being lower than the first rate.

13. The memory of claim 12, further comprising a sample-and-hold circuit coupled to sample the voltage from the driver, wherein a sample taken at the end of the read process, by the sample-and-hold circuit indicates a value read by the read circuit.

14. The memory of claim 11, further comprising:

a row decoder coupled between the driver and the word lines, wherein during the read process, the row decoder connects the driver to the selected word line; and

a column decoder coupled between the sense circuitry and the bit lines, wherein during the read process, the column decoder connects the sense circuit to a selected bit line.

15. The memory of claim 11, wherein the memory stores analog values, each analog value being indicated by a threshold voltage of a memory cell in the array.

16. The memory of claim 11, wherein the memory stores digital values, wherein a threshold voltage of a memory cell in the array indicates multiple bits for a stored digital value.

17. The memory of claim 11, wherein the sense circuit comprises:

a reference column which is in the array and contains memory cells having a lowest possible threshold voltage for memory cells in the array;

a first bias circuit which during the read process is connected to a bit line for the reference column;

a second bias circuit which during the read process is connected to the selected bit line; and

a differential amplifier having a first input terminal and a second terminal respectively coupled to a first node in the first bias circuit and a second node in the second bias circuit, wherein the differential amplifier generates the sense signal.

18. The memory of claim 17, wherein:

the first bias circuit comprises a first transistor coupled between a supply voltage and the bit line for the reference column; and

the second bias circuit comprises a second transistor coupled between the supply voltage and the selected bit line, wherein

a gate and drain of the first transistor are coupled to each other and to a gate of the second transistor so that current on the bit line for the reference column controls the conductivity of the second transistor.

19. The memory of claim 18, wherein the first transistor is larger than the second transistor.

20. A method for reading a memory cell, the method comprising:

executing a series of stages including a first stage and a last stage, wherein each stage comprises;

changing a gate voltage applied to the memory cell; and

ending the stage after changing of the gate voltage causes the memory cell to trip, wherein

for each stage except the first stage, a direction selected for changing the gate voltage during the stage is opposite to a direction selected for changing the gate voltage during a preceding stage;

sampling the gate voltage after the last stage; and

determining from a sampled gate voltage a value read from the memory cell.

21. The method of claim 20, wherein a rate of change in the gate voltage during the last stage is less than a rate of change in the gate voltage during the first stage.

22. The method of claim 20, wherein determining the value read comprises determining an analog value.

23. The method of claim 20, wherein determining the value read comprises determining a multi-bit digital value represented by the sampled gate voltage.

24. The method of claim 20, further comprising:

precharging the gate voltage of the selected memory cell to an initial level;

sensing whether the initial level of the gate voltage causes the selected memory cell to conduct; and

selecting a direction for changing the gate voltage during the first stage, wherein the direction selected for the first stage is determined by whether the initial level of the gate voltage causes the selected memory cell to conduct.

25. The method of claim 24, wherein the initial level is a voltage which is the median of a range of possible threshold voltages for the selected memory cell.