Integrated network switch with flexible serial data packet transfer system

• US 5,748,627 A
• Filed: 06/10/1994
• Issued: 05/05/1998
• Est. Priority Date: 06/10/1994
• Status: Expired due to Term

• Current Assignee: RPX Corporation
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Weir, Steven P.
• Primary Examiner(s): TON, DANG T
• Application Number:
  US08/257,885
• Time in Patent Office: 1,425 Days
• Field of Search: 370/68.1, 370/68, 370/85.6, 370/58.1, 370/67, 370/110.1, 370/60, 370/94.1, 370/84, 370/108, 370/50, 370/104, 370/95.1, 370/95.2, 370/95.3, 370/66, 370/372, 370/373 , 370/374, 370/375-384, 370/389, 370/412, 340/825.5, 340/825.51, 375/371, 375/372, 375/373, 375/374, 395/872, 395/876, 395/874, 395/873, 395/841, 395/842, 395/844, 364/728.02
• US Class Current: 370/384
• CPC Class Codes: H04Q 11/0407 using a stored programme control

Abstract

The present invention relates to an elastic linear buffer. The buffer is arranged in a closed loop, so that upon reaching the last address, the message is wrapped around and writing continues from the first address. Three markers are provided: a write pointer, which indicates the address of the data currently being stored; a head pointer, which indicates the last address of a previously recorded message; and a tail pointer, indicating the address of the data last read from the buffer. When the last bit of a presently received message is recorded, the head pointer is updated to indicate the address of that bit. Thereafter, a message is sent to the CPU which may commence reading of the message just received. Concurrently, a newly received message can be recorded at the addresses following the address of the head pointer up to the address of the tail pointer.

Claims

1. An integrated network switch including ports for connection to peripheral devices, and switching apparatus for selectively switching signals organized in frame format between ports, each port occupying a fixed time slot in the frame format, signalling in each time slot including data signalling, said switch including memory means for receiving and storing said data signalling wherein:

said network switch further includes an elastic store means for storing messages received from said peripheral devices, said elastic store means comprising,

a linear buffer means comprising a plurality of buffer sets, each buffer set having a predefined size determined as a product of a unit buffer size and the number of buffers assigned to a respective set for storing messages received from a peripheral device connected to a respective port,

said switch including means for receiving data signalling in a buffer set and detecting when a complete message has been received,

means for determining and storing the position in the buffer set corresponding to an end of a last complete message received,

means for determining and storing a last position read from the buffer set,

means for reading the buffer set to a position corresponding to the end of the last message received upon detection of a complete message,

means for updating a stored indication of the last position read from the buffer set,

means for updating a stored indication of the position in the buffer set corresponding to the end of the last complete message received, and

means for identifying a next write location in the buffer set at the end of the last complete message received,

wherein said elastic store means stores messages of varying lengths while permitting reading from the buffer set upon receipt of a completed message.

2. An elastic buffer, connected to a read unit, comprising:

a write pointer, indicating a location in said buffer into which data of a presently received message is currently being written;

a head pointer, indicating a location in said buffer corresponding to an end of a previously received and stored message, said head pointer being updated to indicate the location of said write pointer when writing of said previously received message is completed, said reading unit being informed whenever said head unit has been updated to indicate a location of said write pointer so that said read unit can read said presently received message from said buffer;

a tail pointer indicating the last position read by said read unit;

wherein said buffer commences writing of a newly received message after said head unit has been updated to indicate a location of said write pointer;

wherein said buffer is of a closed loop and wherein said buffer can write said presently and newly received messages at locations preceding the location indicated by said tail pointer; and

wherein said memory buffer comprises a memory size equal to M and receiving data having an assigned address from one of addresses designated by a first set defining addresses 0 to M-1 and a second set defining addresses M to 2M-1, said memory buffer ignoring a most significant bit (MSB) of said assigned address to thereby store data assigned an address from said second set in a corresponding location defined by an address from said first set.

3. A memory buffer comprising a memory of a predetermined size defined as M, and receiving data having an assigned address from one of a plurality of addresses designated by a first set defining addresses 0 to M-1, and a second set defining addresses M to 2M-1, said memory buffer ignoring a most significant bit (MSB) of said assigned address to thereby store data assigned an address from said second set in a corresponding location defined by an address from said first set.