Asynchronous transfer mode cell processing system with load multiple instruction and memory write-back

• US 5,748,630 A
• Filed: 05/09/1996
• Issued: 05/05/1998
• Est. Priority Date: 05/09/1996
• Status: Expired due to Term

• Current Assignee: Mindspeed Technologies LLC (MACOM Technology Solutions Holdings, Inc.)
• Original Assignee: Maker Communications, Inc. (Synaptics Incorporated)
• Inventors: Lussier, Daniel J., Bergantino, Paul V.
• Primary Examiner(s): Hsu, Alpus H.
• Assistant Examiner(s): Yao, Kwang B.
• Application Number:
  US08/647,372
• Time in Patent Office: 726 Days
• Field of Search: 370/395, 370/396, 370/397, 370/398, 370/399, 370/412, 370/428, 370/429, 370/382, 370/383, 370/474, 370/476, 395/561, 395/566, 395/401, 395/403, 395/427, 395/474, 395/800, 395/800.01
• US Class Current: 370/412
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 49/108 using shared central buffer
• CPC Class Codes: H04L 49/255 Control mechanisms for ATM switching fabrics

Abstract

Methods and apparatus for processing cells in an asynchronous transfer mode (ATM) communication system. An ATM cell processor includes a load multiple instruction which provides a burst transfer of a data block from an external control memory, and allows the result of a subsequent operation on a loaded value to be automatically written back to the control memory location from which it was previously read. The instruction may specify the address in the control memory of a data block to be retrieved, a destination register in a CPU register file into which the first retrieved halfword of a data block will be loaded, and a total number of halfwords to be retrieved. The instruction includes a link field option which directs the storage of information linking the processor registers which receive the retrieved halfwords to the control memory locations from which the halfwords were read. An automatic memory update feature may be provided in an arithmetic logic unit (ALU) instruction which operates on one or more of the processor registers receiving the halfwords retrieved by the instruction, such that the result of the corresponding ALU operation will be automatically written back to the control memory location or locations which supplied one or more of the operands.

Claims

1. A method of accessing a memory in an asynchronous transfer mode (ATM) cell processing system, the memory including a plurality of memory locations, the method comprising the steps of:

executing a first instruction to load the contents of a subset of the plurality of memory locations into a register file of a processor;

storing a link between a given processor register in the register file and a corresponding memory location the contents of which were loaded into the given register in response to the first instruction; and

executing a second instruction which performs an operation on the contents of the given register, the second instruction including an indicator directing that the result of the operation be automatically written back to the corresponding memory location indicated by the stored link.

2. The method of claim 1 wherein the memory is a control memory which is accessed by the processor via a memory controller.

3. The method of claim 1 wherein the first instruction is a load multiple instruction which specifies an address of the subset of memory locations, a total number of locations to be loaded into the processor register file, and a destination register in the processor register file.

4. The method of claim 1 wherein the second instruction is an arithmetic logic unit (ALU) instruction which specifies the given register, an ALU operation to be performed on the given register, and an indicator that the result of the ALU operation is to be automatically written back to the corresponding memory location.

5. The method of claim 1 wherein the step of storing a link between the given register and the corresponding memory location further includes the step of storing the address of the corresponding memory location in a designated processor register.

6. The method of claim 1 further including the step of waiting a predetermined number of processor cycles before executing a third instruction which accesses the given register in the processor register file.

7. An apparatus for use in an asynchronous transfer mode (ATM) cell processing system, comprising:

a memory including a plurality of memory locations; and

a processor connected to the memory and including a register file having a plurality of registers, the processor executing a first instruction to load the contents of a subset of the plurality of memory locations into the register file, directing storage of a link between a given processor register in the register file and a corresponding memory location the contents of which were loaded into the given register in response to the first instruction, and executing a second instruction which performs an operation on the contents of the given register, the second instruction including an indicator directing that the result of the operation be automatically written back to the corresponding memory location indicated by the stored link.

8. The apparatus of claim 7 wherein the memory is a control memory which is accessed by the processor via a memory controller.

9. The apparatus of claim 7 wherein the first instruction is a load multiple instruction which specifies an address of the subset of memory locations, a total number of locations to be loaded into the processor register file, and a destination register in the processor register file.

10. The apparatus of claim 7 wherein the second instruction is an arithmetic logic unit (ALU) instruction which specifies the given register, an ALU operation to be performed on the given register, and an indicator that the result of the ALU operation is to be automatically written back to the corresponding memory location.

11. The apparatus of claim 7 wherein the processor directs storage of a link between the given register and the corresponding memory location by storing the address of the corresponding memory location in a designated processor register.

12. The apparatus of claim 7 wherein the processor is further operative to execute a third instruction which accesses the given register in the processor register file after a predetermined number of processor cycles.