Clock scan design from sizzle global clock and method therefor

• US 5,748,645 A
• Filed: 05/29/1996
• Issued: 05/05/1998
• Est. Priority Date: 05/29/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Hunter, Craig C., Reininger, Russell A.
• Primary Examiner(s): Nguyen, Hoa T.
• Application Number:
  US08/654,981
• Time in Patent Office: 706 Days
• Field of Search: 371/22.31, 371/22.1, 371/22.2, 371/27.7, 371/22.32, 371/22.34, 371/22.36, 364/270, 364/270.2, 364/270.3, 364/270.4
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318552 Clock circuits details

Abstract

A scan based test methodology generates conventional functional clocks (CLK1 and CLK2) and test clocks (CLKA and CLKB) from a single input clock (GCLK). The methodology allows an integrated circuit (10) designed according to it to be tested at the part'"'"'s operating frequency. Also, the test methodology is compatible with known test methodologies such as level sensitive scan design ("LSSD"). The pre-existing body of test programs and equipment can be used with a circuit incorporating the invention. The single clock requirement also simplifies design.

Claims

1. A single clock scan design circuit for testing a synchronous circuit, the synchronous circuit comprising a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a first test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock, the single clock scan design circuit comprising:

first circuitry receiving a single clock and generating the first test clock therefrom responsive to at least one control signal;

second circuitry receiving the single clock and generating the first functional clock therefrom responsive to the at least one control signal; and

third circuitry receiving the single clock signal and generating the second functional clock from the at least one control signal.

2. The single clock scan design circuit claim 1 wherein one of the plurality of latches is a *L2 further comprising:

fourth circuitry receiving the single clock and generating a second clock therefrom responsive to the at least one control signal.

3. An integrated circuit comprising:

a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a first test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock; and

at least one first clock regenerator, the at least one first clock regenerator receiving a single clock and at least one control signal, the at least one first clock regenerator generating the first functional clock, the first test clock, and the second functional clock.

4. The integrated circuit of claim 3 further comprising:

at least one *L2 latch, the at least one *L2 latch capturing functional data responsive to a second test clock; and

at least one second clock regenerator, the at least one second clock regenerator receiving the single clock and the at least one control signal, the at least one first clock regenerator generating the second test clock.

5. A method of testing an integrated circuit, the integrated circuit comprising a plurality of latches, each one of the plurality of latches receiving a functional input and a scan input and generating an output, each one of the plurality of latches capturing the functional input responsive to the assertion of a first functional clock, each one of the plurality of latches capturing the scan input responsive to the assertion of a test clock, each one of the plurality of latches launching captured data responsive to the assertion of a second functional clock, the method comprising the steps of:

during a first time,

shifting a test vector into the plurality of latches by periodically asserting the test clock, the test clock generated from a single clock and at least one control signal;

during a second time,

applying the test vector stored in the plurality of latches to logic, the outputs of the plurality of latches coupled to the plurality of latches;

during a third time,

capturing an output ("captured output") from the logic by the plurality of latches by asserting the first functional clock, the first functional clock generated from the single clock and the at least one control signal; and

during a fourth time,

shifting out the captured output from the plurality of latches.

6. The method of claim 5 wherein the step of shifting a test vector comprises the step of:

periodically asserting the test clock and the second functional clock.

7. The method of claim 6 wherein the step of capturing an output comprises the step of:

periodically asserting the first functional clock and the second functional clock.

8. The method of claim 5 wherein the step of capturing an output comprises the step of:

periodically asserting the first functional clock and the second functional clock.