Apparatus for detecting and correcting cyclic redundancy check errors

• US 5,748,652 A
• Filed: 06/14/1996
• Issued: 05/05/1998
• Est. Priority Date: 06/29/1995
• Status: Expired due to Fees

• Current Assignee: Utstarcom Korea Limited
• Original Assignee: SK Hynix Inc.
• Inventors: Kim, Jin-Tae
• Primary Examiner(s): CHUNG, PHUNG M
• Application Number:
  US08/664,002
• Time in Patent Office: 690 Days
• Field of Search: 371/53, 371/30, 371/37.6, 371/37.7, 371/67.1, 371/68.1
• US Class Current: 714/807
• CPC Class Codes: H03M 13/09 Error detection only, e.g. using cyclic redundancy check [CRC] codes or single parity bit

Abstract

A cyclic redundancy check (CRC) circuit for detecting and correcting errors in a data stream uses a decoder and a serial-to-parallel buffer to shorten arithmetic operation time. The CRC circuit includes a first gate for switching a serial input data stream into a syndrome register section, and a buffer register for converting the serial input data to a parallel data. The syndrome register section forms redundancies for input data stream. An OR gate receives data from the syndrome register section to enable a decoder if the syndrome register section detects an error in the data stream. The decoder decodes the output from the syndrome register section. The output of the decoder is exclusively-ORed with the input data in the parallel shift register. A latch circuit thereafter outputs a corrected serial data stream.

Claims

1. An apparatus for detecting and correcting cyclic redundancy check (CRC) errors, comprising:

a first gate for switching an input data;

a buffer register for receiving the input data and outputting the input data in parallel;

a syndrome register section including a plurality of syndrome registers for forming redundancies for an output data of said first gate;

an OR gate for receiving data from said syndrome register section to produce an enable signal;

a decoder receiving said enable signal from said OR gate, said decoder for decoding said data from said syndrome register;

a plurality of exclusive-OR (Ex-OR) gates for receiving outputs of said buffer register and said decoder and performing Ex-OR arithmetic operations; and

a latching section for latching outputs of said Ex-OR gates.

2. The apparatus as claimed in claim 1, wherein said syndrome register section comprises a plurality of syndrome registers.

3. The apparatus as claimed in claim 1, wherein if outputs of the plurality of said syndrome registers are all "0", then no error is detected and said OR gate disables said decoder.

4. The apparatus as claimed in claim 1, wherein said decoder and said latching section respectively have a same number of input terminals.

5. The apparatus as claimed in claim 1, wherein a state of said syndrome register section and the consequent output of said decoder are calculated from a mapping table based on a parity check matrix.

6. A cyclic redundancy check (CRC) circuit, comprising:

a buffer register for storing bits of a serial input data that may contain an error and outputting said serial input data as parallel input data;

a plurality of serially connected syndrome registers for creating redundant data from said serial input data;

a decoder for decoding an output from said plurality of serially connected syndrome registers;

an OR gate for enabling said decoder if any of said a plurality of serially connected syndrome registers are active; and

exclusive OR means for performing an exclusive OR function on each bit of said parallel input data with an output of said decoder when said decoder is enabled, wherein a result of said exclusive OR function corrects errors in the serially input data.

7. A cyclic redundancy check (CRC) circuit as recited in claim 6 wherein said plurality of serially connected syndrome registers comprise a most significant bit register and a least significant bit register,

wherein said least significant bit register receives as an input said serial input data exclusively ORed with an output of said most significant bit register and,

wherein said most significant bit register receives as an input an output of a previous one of said plurality of serially connected syndrome registers exclusively ORed with said output of said most significant bit register.

8. A cyclic redundancy check (CRC) circuit as recited in claim 7 wherein said decoder decodes said output from said plurality of serially connected syndrome registers according to a parity check matrix.

9. A cyclic redundancy check (CRC) circuit as recited in claim 6 further comprising a latch circuit for latching an output of said exclusive OR means as a serial data stream.