Apparatus for detecting and correcting cyclic redundancy check errors
First Claim
1. An apparatus for detecting and correcting cyclic redundancy check (CRC) errors, comprising:
- a first gate for switching an input data;
a buffer register for receiving the input data and outputting the input data in parallel;
a syndrome register section including a plurality of syndrome registers for forming redundancies for an output data of said first gate;
an OR gate for receiving data from said syndrome register section to produce an enable signal;
a decoder receiving said enable signal from said OR gate, said decoder for decoding said data from said syndrome register;
a plurality of exclusive-OR (Ex-OR) gates for receiving outputs of said buffer register and said decoder and performing Ex-OR arithmetic operations; and
a latching section for latching outputs of said Ex-OR gates.
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Accused Products
Abstract
A cyclic redundancy check (CRC) circuit for detecting and correcting errors in a data stream uses a decoder and a serial-to-parallel buffer to shorten arithmetic operation time. The CRC circuit includes a first gate for switching a serial input data stream into a syndrome register section, and a buffer register for converting the serial input data to a parallel data. The syndrome register section forms redundancies for input data stream. An OR gate receives data from the syndrome register section to enable a decoder if the syndrome register section detects an error in the data stream. The decoder decodes the output from the syndrome register section. The output of the decoder is exclusively-ORed with the input data in the parallel shift register. A latch circuit thereafter outputs a corrected serial data stream.
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Citations
9 Claims
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1. An apparatus for detecting and correcting cyclic redundancy check (CRC) errors, comprising:
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a first gate for switching an input data; a buffer register for receiving the input data and outputting the input data in parallel; a syndrome register section including a plurality of syndrome registers for forming redundancies for an output data of said first gate; an OR gate for receiving data from said syndrome register section to produce an enable signal; a decoder receiving said enable signal from said OR gate, said decoder for decoding said data from said syndrome register; a plurality of exclusive-OR (Ex-OR) gates for receiving outputs of said buffer register and said decoder and performing Ex-OR arithmetic operations; and a latching section for latching outputs of said Ex-OR gates. - View Dependent Claims (2, 3, 4, 5)
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6. A cyclic redundancy check (CRC) circuit, comprising:
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a buffer register for storing bits of a serial input data that may contain an error and outputting said serial input data as parallel input data; a plurality of serially connected syndrome registers for creating redundant data from said serial input data; a decoder for decoding an output from said plurality of serially connected syndrome registers; an OR gate for enabling said decoder if any of said a plurality of serially connected syndrome registers are active; and exclusive OR means for performing an exclusive OR function on each bit of said parallel input data with an output of said decoder when said decoder is enabled, wherein a result of said exclusive OR function corrects errors in the serially input data. - View Dependent Claims (7, 8, 9)
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Specification