Quantization of input vectors and without rearrangement of vector elements of a candidate vector

• US 5,748,839 A
• Filed: 04/21/1995
• Issued: 05/05/1998
• Est. Priority Date: 04/21/1994
• Status: Expired due to Fees

• Current Assignee: NEC Corporation
• Original Assignee: NEC Corporation
• Inventors: Serizawa, Masahiro
• Primary Examiner(s): MacDonald, Allen R.
• Assistant Examiner(s): CHAWAN, VIJAY B
• Application Number:
  US08/426,649
• Time in Patent Office: 1,110 Days
• Field of Search: 381/36, 381/35, 381/40, 381/43, 381/49, 395/2.31, 395/29, 395/2.28, 395/2.32, 395/2.3
• US Class Current: 704/222
• CPC Class Codes: G06T 9/008 Vector quantisation
• CPC Class Codes: G10L 19/12 the excitation function being a code excitation, e.g. in code excited linear prediction [CELP] vocoders
• CPC Class Codes: H03M 7/3082 Vector coding for television signals, see H04N19/94

Abstract

For quantizing input vectors into output codes with reference to quantization vectors with reduction of a memory capacity, a vector quantizer device comprises a rearranging unit (21, 23) between a codebook circuit (17) preliminarily loaded, in accordance with codebook indexes, with code vectors selected from the quantization vectors to produce at least one candidate vector in response to a current index and a distance calculator (15) for calculating, between each input vector and comparison vectors given by the candidate vector, distance values for supply to an evaluation circuit (19) for producing a selected index indicative of one of the comparison vectors that minimizes the distance values and for successively producing the output codes with the selected index used as each output code without or with addition of a rearrangement index. When the rearrangement index is and is not added, the rearranging circuit produces the candidate vector in each comparison vector as an unchanged vector and as a rearranged vector in which vector elements of the candidate vector are rearranged, respectively. The rearranging unit may rearrange the candidate vector in compliance with a single predetermined rule or with rules preliminarily stored in a rearrangement table circuit (23) in accordance with table indexes with one of the rules delivered to a rearranging circuit (21) in response to the rearrangement index.

Claims

1. A vector quantizing method of quantizing input vectors into output codes, said vector quantizing method comprising the steps of:

preparing a codebook circuit loaded with code vectors in accordance with codebook indexes with each code vector composed of a predetermined number of vector elements,

producing at least one candidate vector of said code vectors in response to a current index selected from said codebook indexes for each of said input vectors,

calculating distances between said each of input vectors and comparison vectors given by said at least one candidate vector to produce distance values representative of said distances, and

evaluating said distance values to select one of said comparison vectors as a selected vector that minimizes said distance values, said evaluating step producing a selected index indicative of said selected vector to successively produce said output codes with said selected index used as each output code,

wherein said vector quantizing method comprises the step of;

using, in said comparison vectors, (1) said at least one candidate vector as an unchanged vector without rearrangement of its vector elements and (2) said at least one candidate vector as a rearranged vector with rearrangement of its vector elements, in response to a rearrangement index,

wherein said evaluating step produces said selected index with no change of and with addition of said rearrangement index to said current index when said selected vector is said unchanged and said rearranged vectors, respectively.

2. A vector quantizing method as claimed in claim 1, wherein:

said vector quantizing method further comprises the step of;

preparing a rearrangement table circuit loaded, in accordance with table indexes, with common manners of converting said at least one candidate vector to said rearranged vector when said current index selects each candidate vector from predetermined ones of said code vectors, and

said evaluating step produces one of said table indexes as said rearrangement index.

3. A vector quanitizing method as claimed in claim 2, wherein:

said vector quantizing method further comprises the step of;

analyzing characteristics of each input vector to produce a result of analysis, and

said rearrangement table circuit makes said using step use said at least one candidate vector as said rearranged vector in compliance with one of said common manners of converting that is specified by said result of analysis.

4. A vector quantizing method as claimed in claim 2, wherein:

each input vector represents a succession of either a consonant and a vowel and a consonant,

said codebook circuit preparing step makes each code vector represent the succession of a consonant and a vowel,

said vector quantizing method further comprises the step of;

analyzing each input vector to judge whether said each of input vectors represents the succession of a consonant and a vowel or of a vowel and a consonant,

said analyzing step makes said rearrangement table circuit select said respectfully rearranged vector with the succession of the last-mentioned vowel and the last-mentioned consonant when said analyzing step judges that each of input vectors represents the succession of a vowel and a consonant.

5. A vector quantizing method as claimed in claim 2, wherein said vector quantizing method further comprises the step of preliminarily training said rearrangement table circuit by using a plurality of training vectors which include said input vectors.

6. A vector quantizing method as claimed in claim 1, wherein said using step uses, in said comparison vectors, said at least one candidate vector with its vector elements rearranged into said rearranged vector in accordance with a single rule alone when said current index selects said at least one candidate vector from predetermined ones of said code vectors.

7. A vector quantizing method as claimed in claim 6, wherein said vector quantizing method further comprises the step of:

preliminary training said using step by using a plurality of training vectors which include said input vectors.

8. A vector quantizer device for quantizing input vectors into output codes, said vector quantizer device comprising:

a codebook circuit preliminary loaded with code vectors in accordance with codebook indexes with each code vector composed of a predetermined number of vector elements to produce at least one candidate vector of said code vectors in response to a current index selected from said codebook indexes for each of said input vectors,

a distance calculator for calculating distances between said each of input vectors and comparison vectors given by said at least one candidate vector to produce distance values representative of said distances, and

an evaluation circuit for evaluating said distance values to select one of said comparison vectors as a selected vector that minimizes said distance values, said evaluation circuit producing a selected index indicative of said selected vector to successively produce said output codes with said selected index used as each output code,

wherein said vector quantizer device comprises vector rearranging means between said codebook circuit and said distance calculator for using in said comparison vectors said at least one candidate vector as an unchanged vector without rearrangement of its vector elements and said at least one candidate vector as a rearranged vector with rearrangement of its vector elements in response to a rearrangement index, said evaluation circuit producing said selected index with no change of and with addition of said rearrangement index to said current index when said selected vector is said unchanged and said rearranged vectors, respectively.

9. A vector quantizer device as claimed in claim 8, wherein said vector rearranging means comprises:

a rearrangement table circuit connected to said evaluation circuit and preliminarily loaded, in accordance with table indexes, with manners of rearrangement in which each candidate vector is rearranged into said rearranged vector in one of said manners of rearrangement that is specified among said table indexes by said rearrangement index; and

a table dependent rearranging circuit connected to said codebook circuit, to said distance calculator, and to said rearrangement table circuit for rearranging said at least one candidate vector into said rearranged vector in said one of manners of rearrangement.

10. A vector quantizer device as claimed in claim 9, wherein:

said rearrangement table circuit is preliminary loaded, in accordance with said table indexes and in correspondence at least to predetermined ones of said code vectors, with common manners of rearrangement, each of said common manners of rearrangement being a manner of rearrangement in common to respective parts of said predetermined ones of code vectors, each of said common manners of rearrangement that is selected being common to a part of said predetermined ones of code vectors; and

said table dependent rearranging circuit rearranging said at least one candidate vector into said rearranged vector in one of said common manners that is specified among said table indexes by said rearrangement index when said at least one candidate vector is one of said predetermined ones of code vectors that is specified by said current index in one of said respective parts.

11. A vector quantizer device as claimed in claim 10, wherein said vector quantizer device further comprises a table training circuit connected to said rearrangement table circuit for training said rearrangement table circuit for production of said one of common manners as an optimum manner of rearrangement in response to a plurality of training vectors which include said input vectors.

12. A vector quantizer device as claimed in claim 11, wherein said vector quantizer device further comprises a table training circuit connected to said rearrangement table circuit for training said rearrangement table circuit for production of said one of manners of rearrangement as an optimum manner of rearrangement in response to a plurality of training vectors which include said input vectors.

13. A vector quantizer device as claimed in claim 10, wherein:

said vector quantizer device further comprises an input vector analyzer for analyzing characteristics of each input vector to produce a result of analysis;

said rearrangement table circuit being connected to said input vector analyzer and made by said result of analysis to supply said table dependent rearranging circuit with one of said common manners that is specified in response to said result of analysis.

14. A vector quantizer device as claimed in claim 9, each input vector representing a succession of either a consonant and a vowel or a vowel and a consonant, each code vector representing in said codebook circuit the succession of a consonant and a vowel, wherein:

said vector quantizer device further comprises an input vector analyzer for analyzing each input vector to judge whether said each of input vectors represents the succession of a consonant and a vowel or of a vowel and a consonant, said input vector analyzer producing mode zero and one signals when said input vector analyzer judges that said each of input vectors represents the succession of a consonant and a vowel and of a vowel and a consonant, respectively;

said rearrangement table circuit being connected to said input vector analyzer and made by said mode zero and one signals to be quiescent and to produce one of said manners of rearrangement in response to said rearrangement index;

said table dependent rearranging circuit using said at least one candidate vector as said unchanged vector and as said rearranged vector with said rearranged vector made to represent the succession of the last-mentioned vowel and the last-mentioned consonant when said rearrangement table circuit is quiescent and produces the last-mentioned one of manners of rearrangement, respectively.

15. A vector quantizer device as claimed in claim 8, wherein said vector rearranging means comprises a single rule rearranging circuit connected to said evaluation circuit, to said codebook circuit, and to said distance calculator for deciding in response to said current index without and with addition of said rearrangement index that each candidate vector should be used as said unchanged vector and, in compliance with a single predetermined rule, as said rearranged vector, respectively, said each candidate vector being produced from one of said code vectors that is specified by said current index.

16. A vector quantizer device as claimed in claim 15, said vector elements being arranged in each code vector in a predetermined order, wherein said single predetermined rule is for inverting said vector elements in said rearranged vector into an inverted order relative to said predetermined order.

17. A vector quantizer device as claimed in claim 15, wherein:

said vector quantizer device further comprises a rule training circuit, connected to said single rule rearranging circuits for training said single predetermined rule for production of said rearranged vector in compliance with an optimum rule of rearrangement, and in response to a plurality of training vectors which includes said input vectors.