Neural processor comprising distributed synaptic cells

• US 5,748,849 A
• Filed: 01/06/1997
• Issued: 05/05/1998
• Est. Priority Date: 02/26/1992
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Gobert, Jean
• Primary Examiner(s): Davis, George B.
• Application Number:
  US08/779,174
• Time in Patent Office: 484 Days
• Field of Search: 395/27, 395/24
• US Class Current: 706/27
• CPC Class Codes: G06N 3/063 using electronic means
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits

Abstract

A neural net has a physical topology independent of its functional topology. Cells, being functional equivalents of synapses, are concatenated to form a unidirectional data path. The cells are connected in parallel to a bus for individual or parallel control The respective synapses contributions to a neuron potential are individually calculated in each respective cell involved. Each cell in the concatenation either is rendered transparent or adds its contribution to the data received from the preceding cell and supplies this sum to the next cell. Preferably, the allocation of the synapses to the cells is programmable.

Claims

1. A neural processor operating to realize the function of neurons interconnected by respective synapses, each synapse forming a part of a particular neuron to evaluate the effect of a respective source neuron on the particular neuron and each synapse being a connection strength between a source and a destination neuron, the particular neuron communicating with a respective destination neuron comprising:

at least one concatenation of respective uniform programmable synaptic cells, the concatenation having an entry and an exit, the concatenation forming a data path between the entry and the exit, the respective uniform programmable synaptic cells each acting as a single one of the respective synapses, the uniform programmable synaptic cells in the concatenation being programmable to aggregate serially at least one group of cells that together form a single neuron, the number of cells in the at least one group also being programmable, each uniform programmable synapse being operative for selectively modifying data in the data path, each uniform programmable synaptic cell having;

a respective data input and a respective data output, the data input of each next one of the cells being connected to the data output of a preceding one of the cells, such that data is transferred along the concatenation,

a respective calculation unit for performing a respective data calculation on data received by the data input and producing selectively modified data at the data output, the calculation unit of each next cell multiplying data received by the next cell with a stored synaptic coefficient and accumulating the multiplication result thereof with a stored or received partial sum produced by a preceding one of the cells;

a respective memory, coupled to the respective calculation unit, for storing data received by the data input or produced as modified data by the calculation unit; and

bus means for communicating a programming instruction to each of the cells, the cells being connected in parallel to the bus means.

2. The neural processor of claim 1, wherein the cells are selectable according to the following modes:

individually; and

in parallel with regard to a shared one of the destination neurons.

3. The neural processor of claim 2, wherein:

each respective cell comprises a respective address unit for receiving and storing a respective programmable address for rendering the cell selectable upon receiving a same respective programmable address supplied by the bus means; and

the respective programmable address comprises at least a first programmable identifier for specifying the source neuron from a respective source-destination neuron pair and/or a second programmable identifier for specifying the destination neuron from the respective pair.

4. The neural processor of claim 3, wherein the respective programmable address is programmed by sending an allocation instruction on the bus means.

5. The neural processor of claim 4, wherein:

each respective cell further comprises a respective allocation unit for providing a first indication or a second indication for specifying, whether or not, respectively, the respective cell is functionally incorporated in the data path by means of a reference address having been introduced into the cell'"'"'s address unit for correlation with the respective address; and

the respective allocation unit of each cell is concatenated to form an allocation path for unidirectional propagation of the allocation instruction to successively allocate a next one of the cells to a further one of the synapses under control of the first indication received from a preceding one of the cells.

6. The neural processor of claim 1, wherein in each cell the respective calculation unit comprises a respective adder and a respective register coupled between an input and an output of the adder, and the calculation unit selectively performs iterative additions to create a respective product.

7. The neural processor of claim 6, wherein the respective calculation unit of a next cell creates a next partial sum.

8. A neural processor according to claim 1 further comprising:

at least one second concatenation of respective uniform programmable synaptic cells, each of the respective cells in the first and second concatenation acting as a respective single one of the synapses, each concatenation producing a respective aggregate sum; and

adding means for linearly combining the respective aggregate sums.

9. A neural net with a processor comprising:

a data input for receiving data, and a data output for supplying data;

a data path between the data input and the data output and comprising a plurality of concatenated uniform cells;

an address bus connected in parallel to the cells for supplying a current address to select one or more of the cells;

the current address comprising a current source neuron identifier, a current destination neuron identifier and control information for controlling processing of the current identifiers by the cells; and

each respective one of the cells comprising;

respective first storage means for storing a respective synaptic coefficient;

respective second storage means for storing a respective neuron state;

respective third storage means for storing a respective source neuron identifier and a respective destination neuron identifier assigned to the respective cell;

respective comparing means for generating a first control signal indicative of comparing the current source neuron identifier with the respective source neuron identifier, and a second control signal indicative of comparing the current destination neuron identifier with the respective destination neuron identifier;

each respective one of the cells comprises processing means for selectively processing data received from a next preceding cell under control of the current address by either passing on the data after operating thereon using the respective synaptic coefficient and the respective neuron state, or passing the data on unmodified to a next successive cell; and

control means connected between the comparing means and the processing means for control of the processing dependent on the first and second control signals and on the control information supplied in the current address.

10. The neural net of claim 9, wherein:

the processor comprises a further data paths in parallel with the data path between the data input and the data output, and comprising a further plurality of further concatenated uniform cells; and

the address bus is connected in parallel to the cells and further cells.

11. The neural net of claim 10, wherein the processor comprises an adder with a first adder input connected to an output of the concatenation of cells and a second input connected to an output of the concatenation of further cells and having an adder output coupled to the data output.

12. A neural processor operating to realize the function of neurons interconnected by respective synapses, a synapses synapse being a connection strength between a source and a destination neurons neuron, said neural processor comprising:

at least one concatenation of respective uniform synaptic cells, to aggregate serially separate source neurons contributions to obtain a whole contribution brought by those source neurons connected onto one destination neuron, the concatenation having an entry and an exit, the concatenation forming a data path between the entry and the exit, one data path comprising a programmable number of synaptic cells, each synaptic cell comprising;

a respective data input and a respective data output, the data input of each next one of the cells being connected to the data output of a preceding one of the cells, such that data is transferred along the concatenation,

a respective calculation unit for performing a respective data calculation, and

a respective memory, coupled to the respective calculation unit, for storing data; and

bus means for communicating an instruction, the cells being connected in parallel to the bus means,

each respective cell comprising a respective address unit for receiving and storing a respective programmable address for rendering the cell selectable upon receiving a same respective programmable address supplied by the bus means,

the respective programmable address comprising at least a first;

programmable identifier for specifying the source neuron from a respective source-destination neuron pair and/or a second programmable identifier for specifying the destination neuron from the respective pair, and

the respective programmable address being programmed by sending an allocation instruction on the bus means.