Direct replacement cell fault tolerant architecture
First Claim
1. A data processing system containing a monolithic network of cells with sufficient redundancy to allow an array of cells to be organized where said array would, if made with the same processes but without spare cells, contain on the average a plurality of defective cells, with a yield in excess of 50% of arrays where all defective array cells are logically replaced by correctly functioning spare cells, where said sufficient redundancy includes a spare cell arrangement that provides a specified number of spare cells that are potential replacements for any array cell, with fewer than that specified number of times as many spare cells as array cells in the network as a whole;
- where each spare cell that replaces an array cell duplicates or utilizes every internal function and every external connection of said array cell so that said spare cell interacts with the rest of said data processing system in a manner logically identical to the way said array cell would have had it not been defective; and
where said array cells also have at least one of the following properties;
(a) any array cell is directly addressable through a single off/on addressing signal for each physical array dimension, said addressing signal for a physical dimension traveling through a carrier that propagates said addressing signal directly to each array cell at the same index as said array cell in said physical dimension, said array cell receiving said addressing signal through a connection dedicated to said array cell;
(b) each array cell has input means for receiving a signal directly from at least one neighboring array cell and output means for sending a signal directly to at least one other neighboring array cell in each of at least three total dimensions, at least two of which are physical dimensions, with said signals between a pair of neighboring array cells being sent through a dedicated carrier connecting solely said pair of array cells or said pair of array cells and their potential replacements;
(c) each array cell has direct optical output means for sending an optical output signal directly external to said data processing system, where said direct optical output means are dedicated solely to said array cell or said array cell and its potential replacements, where the carrier or carriers through which the controlling signals for said direct optical output means are sent to said direct optical output means are dedicated solely to said array cell or said array cell and its potential replacements; and
where the replacement of an array cell by one of said potential replacements does not change the position of the optical output that would have come from said replaced array cell by more than 50 microns.
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Accused Products
Abstract
A data processing system containing a monolithic network of cells with sufficient redundancy provided through direct logical replacement of defective cells by spare cells to allow a large monolithic array of cells without uncorrectable defects to be organized, where the cells have a variety of useful properties. The data processing system according to the present invention overcomes the chip-size limit and off-chip connection bottlenecks of chip-based architectures, the von Neumann bottleneck of uniprocessor architectures, the memory and I/O bottlenecks of parallel processing architectures, and the input bandwidth bottleneck of high-resolution displays, and supports integration of up to an entire massively parallel data processing system into a single monolithic entity.
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Citations
30 Claims
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1. A data processing system containing a monolithic network of cells with sufficient redundancy to allow an array of cells to be organized where said array would, if made with the same processes but without spare cells, contain on the average a plurality of defective cells, with a yield in excess of 50% of arrays where all defective array cells are logically replaced by correctly functioning spare cells, where said sufficient redundancy includes a spare cell arrangement that provides a specified number of spare cells that are potential replacements for any array cell, with fewer than that specified number of times as many spare cells as array cells in the network as a whole;
- where each spare cell that replaces an array cell duplicates or utilizes every internal function and every external connection of said array cell so that said spare cell interacts with the rest of said data processing system in a manner logically identical to the way said array cell would have had it not been defective; and
where said array cells also have at least one of the following properties;(a) any array cell is directly addressable through a single off/on addressing signal for each physical array dimension, said addressing signal for a physical dimension traveling through a carrier that propagates said addressing signal directly to each array cell at the same index as said array cell in said physical dimension, said array cell receiving said addressing signal through a connection dedicated to said array cell; (b) each array cell has input means for receiving a signal directly from at least one neighboring array cell and output means for sending a signal directly to at least one other neighboring array cell in each of at least three total dimensions, at least two of which are physical dimensions, with said signals between a pair of neighboring array cells being sent through a dedicated carrier connecting solely said pair of array cells or said pair of array cells and their potential replacements; (c) each array cell has direct optical output means for sending an optical output signal directly external to said data processing system, where said direct optical output means are dedicated solely to said array cell or said array cell and its potential replacements, where the carrier or carriers through which the controlling signals for said direct optical output means are sent to said direct optical output means are dedicated solely to said array cell or said array cell and its potential replacements; and
where the replacement of an array cell by one of said potential replacements does not change the position of the optical output that would have come from said replaced array cell by more than 50 microns. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21)
- where each spare cell that replaces an array cell duplicates or utilizes every internal function and every external connection of said array cell so that said spare cell interacts with the rest of said data processing system in a manner logically identical to the way said array cell would have had it not been defective; and
- 22. A data processing system containing a monolithic array of cells, where fault tolerance is provided by spare cells and means for said spare cells to logically replace defective array cells, where said system contains more spare cells than there are defective array cells so that some spare cells are not assigned to replace defective array cells, where said array cells and any assigned spare cells are used for processing a parallel task and where a control program uses a plurality of said unassigned spare cells to cooperatively execute a single serial task.
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24. A data processing system containing a monolithic array of cells, where fault tolerance is provided by spare cells and means for said spare cells to logically replace defective array cells, where said system contains more spare cells than there are defective array cells so that some spare cells are not assigned to replace defective array cells, where said array cells and any assigned spare cells are used for processing a parallel task or as directly addressable memory, and where a control program uses a plurality of said unassigned spare cells as indirectly addressed memory said memory comprising a RAM disk, disk cache, I/O buffer and/or swap space.
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25. A data processing system containing a monolithic array of cells where the monolithic region containing said array of cells also contain at least one spare cell and means for that spare cell to replace at least one replaceable array cell should said replaceable array cell prove defective, where each array cell has direct optical output means for sending an optical output signal directly external to said data processing system, said direct optical output means being dedicated solely to that array cell or that array cell and its potential replacement or replacements, with the controlling signals for said output means being sent to said output means through one or more carriers dedicated solely to that array cell or that array cell and its potential replacement or replacements;
- where said direct optical output means form the pixels of a human-readable display; and
where the replacement of said replaceable array cell by said spare cell does not induce a change of more than 50 microns in the position of the direct optical output that would have come from said replaceable array cell. - View Dependent Claims (26, 27, 28, 29, 30)
- where said direct optical output means form the pixels of a human-readable display; and
Specification