Digital logic simulation/emulation system
First Claim
1. A digital logic simulation/emulation system comprising:
- a computer program digital-logic simulation process executed by a digital computer for modeling a digital logic system;
a hardware pod that;
is adapted for being coupled to a digital logic circuit;
includes a configurable-logic integrated circuit ("IC") which is arranged to include a plurality of stimulus/response cells for providing stimulus signals to the digital logic circuit during a stimulation-response cycle, and for receiving responses from the digital logic circuit during the stimulation-response cycle; and
further includes a communication port for receiving stimulation-control data to be transmitted to the configurable-logic IC for controlling stimulation of the digital logic circuit by the configurable-logic IC during the stimulation-response cycle, and for receiving for transmission from said hardware pod response data which the configurable-logic IC receives from the digital logic circuit in response to stimulation thereof during the stimulation-response cycle; and
a server process, coupled both to said digital-logic simulation process and to said hardware pod, for exchanging stimulation-control data and response data between said digital-logic simulation process and said hardware pod, whereby said digital-logic simulation process may transmit stimulation-control data through said server process to said hardware pod for controlling stimulation of the digital logic circuit by the stimulus/response cells during the stimulation-response cycle, and whereby said digital-logic simulation process may receive from said hardware pod through said server process response data from stimulus/response cells of the configurable-logic IC that reports the response of the digital logic circuit to stimulation during the stimulation-response cycle.
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Accused Products
Abstract
A digital logic simulation/emulation system, that includes a hardware pod having a configurable-logic IC arranged to provide a plurality of stimulus/response cells, is adapted for coupling to a digital logic circuit. The stimulus/response cells, which provide stimulus signals to the digital logic circuit, connect to form a shift-register for downloading stimulus-control data, and for uploading response data during a stimulation-response cycle. A logic-configuration library stores configuration-data for establishing a bit-slice architecture for the stimulus/response cells. To facilitate preparing the configuration-data, the system also includes a configurable-logic-specification process having a GUI user interface. The logic-specification process assigns pre-established, bit-slice configuration data for each logic-function cell to specific locations throughout a configurable-logic IC to achieve swift compilation of configuration data.
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Citations
40 Claims
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1. A digital logic simulation/emulation system comprising:
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a computer program digital-logic simulation process executed by a digital computer for modeling a digital logic system; a hardware pod that; is adapted for being coupled to a digital logic circuit; includes a configurable-logic integrated circuit ("IC") which is arranged to include a plurality of stimulus/response cells for providing stimulus signals to the digital logic circuit during a stimulation-response cycle, and for receiving responses from the digital logic circuit during the stimulation-response cycle; and further includes a communication port for receiving stimulation-control data to be transmitted to the configurable-logic IC for controlling stimulation of the digital logic circuit by the configurable-logic IC during the stimulation-response cycle, and for receiving for transmission from said hardware pod response data which the configurable-logic IC receives from the digital logic circuit in response to stimulation thereof during the stimulation-response cycle; and a server process, coupled both to said digital-logic simulation process and to said hardware pod, for exchanging stimulation-control data and response data between said digital-logic simulation process and said hardware pod, whereby said digital-logic simulation process may transmit stimulation-control data through said server process to said hardware pod for controlling stimulation of the digital logic circuit by the stimulus/response cells during the stimulation-response cycle, and whereby said digital-logic simulation process may receive from said hardware pod through said server process response data from stimulus/response cells of the configurable-logic IC that reports the response of the digital logic circuit to stimulation during the stimulation-response cycle. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A hardware pod that is adapted for being coupled to a digital logic circuit, and is also adapted for incorporation into a digital logic simulation/emulation system that includes a computer program digital-logic simulation process executed by a digital computer for modeling a digital logic system, the digital logic simulation/emulation system also including a server process, coupled both to the digital-logic simulation process and to the hardware pod, for exchanging stimulation-control data and response data between the digital-logic simulation process and the hardware pod, the hardware pod comprising:
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a configurable-logic IC which is arranged to include a plurality of stimulus/response cells for providing stimulus signals to the digital logic circuit during a stimulation-response cycle, and for receiving responses from the digital logic circuit during the stimulation-response cycle; and a communication port for receiving stimulation-control data to be transmitted to the configurable-logic IC for controlling stimulation of the digital logic circuit by the configurable-logic IC during the stimulation-response cycle, and for receiving for transmission from the hardware pod response data which the configurable-logic IC receives from the digital logic circuit in response to stimulation thereof during the stimulation-response cycle; whereby the digital-logic simulation process may transmit stimulation-control data through the server process to the hardware pod for controlling stimulation of the digital logic circuit by the stimulus/response cells during the stimulation-response cycle, and whereby the digital-logic simulation process may receive from the hardware pod through the server process response data from stimulus/response cells of the configurable-logic IC that reports the response of the digital logic circuit to stimulation during the stimulation-response cycle. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method for swiftly determining configuration data to be used for configuring a configurable-logic IC for performing specified digital logic functions, the configurable-logic IC including an array of configurable-logic cells that may be logically interconnected by the configuration data to perform specific digital logic functions, the method comprising the steps of:
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determining, for a plurality of logic-function cells to be established within the configurable-logic IC, a digital logic function to be performed by each such logic-function cell; retrieving from a configurable-logic cell-library, which stores configuration data that specifies various different types of individual logic-function cells, configuration data for each logic-function cell in the plurality of logic-function cells, the configuration data retrieved for each logic-function cell specifying a pre-established interconnection of several configurable-logic cells included in the configurable-logic IC which, upon loading of such configuration data into a configurable-logic IC, establishes by interconnecting several configurable-logic cells a digital logic circuit within the configurable-logic IC that performs the digital logic functions specified for that logic-function cell; and determining the configuration data to be used for configuring a configurable-logic IC merely by assigning to specific locations throughout the configurable-logic IC the configuration data retrieved from the configurable-logic cell-library for each of the logic-function cells. - View Dependent Claims (22, 23, 24, 25, 26)
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27. A faster-performance digital logic simulation/emulation system comprising:
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stimulation-control data that specifies stimulation-response-cycle data to be to be applied to a digital logic circuit during stimulation-response cycles; a hardware pod that; is adapted for receiving the stimulation-response-cycle data, and for being coupled to the digital logic circuit; includes a configurable-logic IC which is arranged to include a plurality of stimulus/response cells for providing stimulus signals to the digital logic circuit during the stimulation-response cycles, and for receiving responses from the digital logic circuit during the stimulation-response cycles; and further includes a communication port for receiving stimulation-response-cycle data to be transmitted to the configurable-logic IC for controlling stimulation of the digital logic circuit by the configurable-logic IC during the stimulation-response cycles; and a server process, coupled to said hardware pod for supplying stimulation-response-cycle data to said hardware pod, whereby stimulation-response-cycle data supplied by said server process to said hardware pod controls stimulation of the digital logic circuit by the stimulus/response cells during the stimulation-response cycles. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40)
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Specification