Polarity switched data bus for reduced electromagnetic interference

• US 5,748,902 A
• Filed: 07/19/1996
• Issued: 05/05/1998
• Est. Priority Date: 07/19/1996
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Compaq Computer Corporation (HP Inc.)
• Inventors: Podhaisky, Todd D., Dalton, Scott W.
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): Nguyen, Cuong H.
• Application Number:
  US08/684,536
• Time in Patent Office: 655 Days
• Field of Search: 395/200.13, 395/200.18, 395/306, 375/260, 375/288, 375/289, 375/360, 370/464, 370/545, 371/56, 371/55, 364/514 R
• US Class Current: 709/246
• CPC Class Codes: H04L 25/085 Arrangements for reducing interference in line transmission systems, e.g. by differential transmission

Abstract

In a data bus with m data bits, electromagnetic interference is produced by polarity switching the data on that data bus. When two consecutive data items result in a change of over half of the data bits, the polarity of the second data item is switched, and a polarity signal is correspondingly switched on the data bus. When the data is received, it is restored to its original polarity by adjusting the polarity of the received data according to the signal on the polarity line. In this way, the total number of bit transitions between any two data items is reduced to a maximum of m/2.

Claims

1. A system for passing data items of m bits over a data bus with reduced electromagnetic interference, the system comprising:

a data bus with a data polarity line that carries a data polarity signal and with m data lines that carry polarity adjusted data items;

a data transmission circuit coupled to the data bus and receiving the data items, the data transmission circuit including;

storage that holds a first data item of the received data items;

a bit level comparison circuit coupled to the storage and receiving a second data item of the received data items, the bit level comparison circuit providing an indication of whether over m/2 of the bits in the first and second data items are different; and

a polarity adjusted output circuit receiving the first and second data items, having a polarity output and polarity adjusted data outputs, and responsive to the indication of whether over m/2 of the bits in the first and second data items are different, said polarity adjusted output circuit adapted to provide a first polarity signal on its polarity output and a first polarity adjusted data item on its polarity adjusted data outputs at a first polarity corresponding to the first polarity signal, and to provide a second polarity signal on its polarity output and a second polarity adjusted data item on its polarity adjusted data outputs at a second polarity corresponding to the second polarity signal, wherein the polarity adjusted output circuit provides the second polarity signal to indicate the opposite polarity as the first polarity signal in response to the indication indicating that over m/2 bits are different.

2. The system of claim 1, wherein said data transmission circuit is implemented in a single integrated circuit.

3. The system of claim 1, wherein the data items are video data and the data bus is a video data bus, the system further comprising:

a video controller coupled to the data transmission circuit, the video controller providing the data items to the data transmission circuit.

4. The system of claim 1 further comprising:

a decoding receive circuit coupled to the bus and providing decoded received data outputs, the decoding receive circuit providing as the decoded received data the data on the m data fines when a corresponding data polarity signal on the data polarity line is at a first state, and providing as the decoded received data the inverse of the data on the m data lines when the corresponding data polarity signal on the data polarity line is at a second state.

5. The system of claim 4, wherein the data on the m data lines and the corresponding data polarity signal are both present on the data bus at the same time.

6. The system of claim 4, wherein the data bus includes a clock line carrying a clock signal, and wherein the data on the m data lines and the corresponding data polarity signal are offset in time from each other by at least one cycle of the clock signal.

7. The system of claim 4 further comprising:

a video display coupled to said decoding receive circuit, the video display displaying the decoded received data.

8. A computer system for providing video data with reduced EMI, the system comprising:

a processor for executing instructions and writing data to be displayed;

a memory for storing to be displayed;

a video controller coupled to said memory and said processor, said video controller providing m bit video data items corresponding to the data to be displayed;

a data bus with a data polarity line that carries a data polarity signal and with m data lines that carry polarity adjusted data items;

a data transmission circuit coupled to the data bus and receiving the m bit video data items, the data transmission circuit including;

storage that holds a first video data item of the received video data items;

a bit level comparison circuit coupled to the storage and receiving a second video data item of the received video data items, the bit level comparison circuit providing an indication of whether over m/2 of the bits in the first and second video data items are different; and

a polarity adjusted output circuit receiving the first and second video data items, having a polarity output and polarity adjusted data outputs, and responsive to the indication of whether over m/2 of the bits in the first and second video data items are different, said polarity adjusted output circuit adapted to provide a first polarity signal on its polarity output and a first polarity adjusted video data item on its polarity adjusted data outputs at a first polarity corresponding to the first polarity signal, and to provide a second polarity signal on its polarity output and a second polarity adjusted video data item on its polarity adjusted data outputs at a second polarity corresponding to the second polarity signal, wherein the polarity adjusted output circuit provides the second polarity signal to indicate the opposite polarity as the first polarity signal in response to the indication indicating that over m/2 bits are different;

a decoding receive circuit coupled to the bus and providing decoded received video data outputs, the decoding receive circuit providing as the decoded received video data the data on the m data lines when a corresponding data polarity signal on the data polarity line is at a first state, and providing as the decoded received data the inverse of the data on the m data lines when the corresponding data polarity signal on the data polarity line is at a second state; and

a display that receives and displays the decoded received video data.

9. The system of claim 8, wherein said data transmission circuit is implemented in a single integrated circuit.

10. The system of claim 8, wherein the data on the m data lines and the corresponding data polarity signal are both present on the data bus at the same time.

11. The system of claim 8, wherein the data bus includes a clock line carrying a clock signal, and wherein the data on the m data lines and the corresponding data polarity signal are offset in time from each other by at least one cycle of the clock signal.

12. The system of claim 8 further comprising:

a video display coupled to said decoding receive circuit, the video display displaying the decoded received data.

13. A method of reducing EMI over a bus with m data lines and a data polarity line, the method comprising the steps of:

receiving a first data item for transmission over the bus;

transmitting the first data item over the data lines at a first polarity;

transmitting a first polarity signal reflecting the first polarity over the data polarity line;

receiving a second data item for transmission over the bus;

transmitting the second data item over the data lines at a second polarity; and

transmitting a second polarity signal reflecting the second polarity over the data polarity line, wherein the second polarity is the same as the first polarity if no more than m/2 of the bits of the second data item are different from corresponding bits of the first data item, and wherein the second polarity is the opposite of the first polarity if more than m/2 of the bits of the second data item are different from the corresponding bits of the first data item.

14. The method of claim 13, wherein the first data item and the first polarity signal are transmitted simultaneously.

15. A method of displaying video data with reduced EMI in a computer system including a processor;

a video controller, an m data line video cable with a data polarity line, and a video display, comprising the steps of,

providing data to be displayed from the processor;

generating first and second video data items in the video controller responsive to the data to be displayed;

transmitting a first polarity signal and a first polarity adjusted video data item corresponding to the fist video data item at a polarity corresponding to the first polarity signal over the data lines and the data polarity line;

determining whether over m/2 input data, bits in the first and second video data items are different;

providing a second polarity signal at the inverse of the first polarity sign if over m/2 input data bits are different;

transmitting the second polarity signal and a second polarity adjusted video data item corresponding to the second video data item at a polarity corresponding to the second polarity signal;

decoding the transmitted first and second polarity adjusted data items; and

displaying the decoded transmitted first and second polarity adjusted data items.

16. A system for transmitting data over an m bit bus with reduced electromagnetic interference, the system comprising:

a source of m bit data items, including a first m bit data item and a second m bit data item;

a transmitter for transmitting data items over the m bit bus; and

means for determining the number of data transitions between said first data item and said second data item, said means for comparing providing the second data item at an inverted polarity to the means for transmitting if said second data item has greater than m/2 data transitions from said first data item.

17. The system of claim 16, wherein said means for comparing is an application specific integrated circuit with circuitry for comparing the first data item to the second data item.

18. The system of claim 16, wherein said means for comparing is a microprocessor executed routine that compares the first data to the second data item.

19. The system of claim 16 farther comprising:

a means for providing a polarity indication in conjunction with the data bus.

20. The system of claim 19, wherein said means for providing is a separate signal line containing polarity status.

21. A method for reducing electromagnetic interference in a system with an m bit data bus for each of a plurality of succeeding data items, the method comprising the steps of:

receiving a first data item of m bits;

receiving a second data item of m bits;

comparing the number of bit transitions between said second data item and said first data item;

providing an adjusted second data item at the same polarity as said second data item if less than a predetermined number of bit transitions occur, and providing said second corrected data item at an inverted polarity if a greater than the predetermined number of bit transitions occurred;

transmitting said second corrected data item over the bus;

repeating the preceding steps using said second corrected data item as the first data item, and using a next data item as the second data item.

22. A method for reducing electromagnetic interference on a data bus with mbits, comprising the steps of:

receiving a first data item of m bits;

receiving a second data item of m bits;

transmitting said first data item over the bus;

if no more than one-half of the m bits of the second data item are different from corresponding ones of the m bits of the first data item, forming a second item that is equal to the second data item and else forming the second item as corresponding to the second data item but with no more than one-half of the m bits of the second item changing from corresponding ones of the m bits of the first data item; and

transmitting a second item over the bus corresponding to said second data item such that no more than one-half of the m bits of said second item change from the m bits of said first data item.