User-removable central processing unit card for an electrical device
First Claim
1. A user-removable CPU card comprising:
- a substrate having a width approximately the width of a credit card;
a bus bridge memory controller supported by said substrate, said bus bridge memory controller comprising a bus interface unit;
a central processing unit supported by said substrate, said central processing unit being electrically coupled to said bus bridge memory controller;
read-only-memory supported by said substrate, said read-only-memory being electrically coupled by said bus bridge memory controller to said central processing unit;
a first connector supported by said substrate, said first connector being coupled by said bus bridge memory controller to said central processing unit;
dynamic random-access-memory said dynamic random-access-memory being supported by said substrate, said bus bridge memory controller further comprising a memory control unit, said memory control unit coupling said dynamic random-access-memory and said read-only-memory to said central processing unit; and
a plurality of chip select lines coupled to said memory control unit, wherein said memory control unit distinguishes between said read-only-memory and said dynamic random-access-memory by driving a plurality of signals on said plurality of chip select lines;
wherein on insertion of said CPU card through an opening in a housing of an electrical device, said first connector is detachably and electrically coupled with a second connector of a system board enclosed by said housing;
wherein said system board supplies power to said CPU card through said second connector and said first connector on said insertion; and
wherein said bus bridge memory controller passes a first address signal to said first connector on receipt of said first address signal from said central processing unit.
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Accused Products
Abstract
A user-removable CPU card includes a microprocessor and a bus bridge memory controller that allows the use of the microprocessor as a central processing unit of an electrical device (e.g. notebook PC or desktop PC). The user-removable CPU card includes a first connector that can be detachably coupled to a second connector in the electrical device, when the user-removable CPU card is inserted through an opening of the electrical device. When the electrical device is powered up subsequent to such insertion, the microprocessor on the user-removable CPU card functions as the central processing unit. Inclusion of a central processing unit of a computing device on a user-removable CPU card allows easy replacement of the CPU, for example, by simply opening a door and operating an eject mechanism, without disassembly of the housing. Therefore, a user can upgrade to a new central processing unit by simply ejecting a previously inserted user-removable CPU card and inserting a new user-removable CPU card, as easily as switching diskettes in the prior art (except for powering up the electrical device after such switching).
137 Citations
15 Claims
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1. A user-removable CPU card comprising:
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a substrate having a width approximately the width of a credit card; a bus bridge memory controller supported by said substrate, said bus bridge memory controller comprising a bus interface unit; a central processing unit supported by said substrate, said central processing unit being electrically coupled to said bus bridge memory controller; read-only-memory supported by said substrate, said read-only-memory being electrically coupled by said bus bridge memory controller to said central processing unit; a first connector supported by said substrate, said first connector being coupled by said bus bridge memory controller to said central processing unit; dynamic random-access-memory said dynamic random-access-memory being supported by said substrate, said bus bridge memory controller further comprising a memory control unit, said memory control unit coupling said dynamic random-access-memory and said read-only-memory to said central processing unit; and a plurality of chip select lines coupled to said memory control unit, wherein said memory control unit distinguishes between said read-only-memory and said dynamic random-access-memory by driving a plurality of signals on said plurality of chip select lines; wherein on insertion of said CPU card through an opening in a housing of an electrical device, said first connector is detachably and electrically coupled with a second connector of a system board enclosed by said housing; wherein said system board supplies power to said CPU card through said second connector and said first connector on said insertion; and wherein said bus bridge memory controller passes a first address signal to said first connector on receipt of said first address signal from said central processing unit. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A user-removable CPU card comprising:
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a substrate having a width approximately the width of a credit card; a circuit supported by the substrate, the circuit comprising a bus interface unit; a central processing unit supported by the substrate, the central processing unit being electrically coupled to the circuit; a first connector supported by the substrate, the first connector being coupled by the circuit to the central processing unit, read-only-memory supported by the substrate, the read-only-memory being encoded with basic-input-output-system (BIOS) instructions; a memory control unit included in the circuit; and a memory bus that electrically couples the memory control unit to the read-only-memory, the memory bus including a chip select line; wherein the memory control unit drives a signal active on the chip select line thereby to retrieve the BIOS instructions for execution by the central processing unit; wherein on insertion of the CPU card through an opening in a housing of an electrical device, the first connector is detachably and electrically coupled with one of a plurality of connectors of a system board enclosed by the housing; and wherein the circuit passes a first address signal to the first connector on receipt of the first address signal from the central processing unit. - View Dependent Claims (12, 13, 14, 15)
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Specification