Program rewriting method and apparatus for multiprocessor system

• US 5,748,967 A
• Filed: 01/10/1994
• Issued: 05/05/1998
• Est. Priority Date: 01/11/1993
• Status: Expired due to Fees

• Current Assignee: Hitachi, Ltd.
• Original Assignee: Hitachi, Ltd.
• Inventors: Nakamura, Takahiro, Oka, Takafumi
• Primary Examiner(s): Harvey, Jack B.
• Assistant Examiner(s): Seto, Jeffrey K.
• Application Number:
  US08/179,200
• Time in Patent Office: 1,576 Days
• Field of Search: 395/425, 395/775, 395/474, 395/712, 395/200.07, 395/220.08, 395/492, 395/800, 364/147, 364/921, 364/921.2, 365/189.01, 365/189.07, 365/218
• US Class Current: 717/168
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators

Abstract

In at least two microprocessor systems each having a microprocessor, a flash electrically erasable programmable read only memory (EEPROM), and a system bus connected to the microprocessor and the memory, there is disposed a controller between the system buses of the respective systems. The processor of one of the systems rewrites a program in the memory of a remaining system via the system bus of the remaining system.

Claims

1. A method of rewriting, by a first microprocessor in a first microprocessor system, contents of a program memory for a second microprocessor in a second microprocessor system and vice versa, said first microprocessor system including said first microprocessor, a first rewritable program memory for storing therein an executable program for said first microprocessor, and a first system bus connected to said first microprocessor and said first rewritable program memory, and said second microprocessor system including said second microprocessor, a second rewritable program memory for storing therein an executable program for said second microprocessor, and a second system bus connected to said second microprocessor and said second rewritable program memory, said second system bus being separate from said first system bus, said method comprising the steps of:

releasing said second system bus by said second microprocessor, in response to a request from said first microprocessor;

supplying from said first system bus an address on said second system bus thus released under control of said first microprocessor;

reading data of a new program from a common memory connected to said first and second system buses and commonly accessible by said first and second microprocessors under control of said first and second microprocessors;

supplying from said first system bus the data thus read on said second system bus thus released under control of said first microprocessor; and

rewriting the data thus supplied on said second system bus in said second program memory by performing data write operation of said second program memory under control of said first microprocessor.

2. A method according to claim 1, wherein said rewriting step further includes the steps of:

reading, under control of said first microprocessor, data after rewrite operation of said second rewritable program memory on said second system bus which has been released; and

transferring, under control of said first microprocessor, the data after rewrite operation thus read to said first system bus, thereby confirming correct rewrite operation by said first microprocessor.

3. A method according to claim 1, wherein said second program memory is an electrically erasable read only memory.

4. An apparatus for rewriting, by a first microprocessor in a first microprocessor system, contents of a program memory for a second microprocessor in a second microprocessor system and vice versa, comprising:

said first microprocessor system, including said first microprocessor, further includes a first rewritable program memory for storing therein an executable program for said first microprocessor, and a first system bus connected to said first microprocessor and said first rewritable program memory;

said second microprocessor system, including said second microprocessor, further includes a second rewritable program memory for storing therein an executable program for said second microprocessor, and a second system bus connected to said second microprocessor and said second rewritable program memory, said second system bus being separate from said first system bus;

storage means connected to said first and second system buses, for storing therein a new program for a rewrite operation, said storage means being commonly accessible for a read operation from said first and second microprocessors through said first and second system buses, respectively under control of said first and second microprocessors;

a request line for transmitting a request from said first microprocessor to said second microprocessor to cause said second microprocessor to release said second system bus; and

means connected between said first and second system buses for replacing, in accordance with execution under control of said first microprocessor, contents of said second rewritable program memory with contents of said storage means by reading data from said storage means on said first system bus and transferring the data thus read to said second system bus after said second system bus is released by the request from said first microprocessor.

5. An apparatus according to claim 4, wherein said replacing means includes:

means, operative after said second microprocessor releases said second system bus in response to the request from said first microprocessor, for supplying from said first system bus an address on said second system bus which has been released, under control of said first microprocessor;

means for reading, under control of said first microprocessor, data from said storage means on said first system bus, and transferring the data thus read to said second system bus which has been released; and

means for rewriting, under control of said first microprocessor, the data thus transferred on said second system bus in said second rewritable program memory.

6. An apparatus according to claim 5, wherein said rewriting means includes:

means for reading, under control of said first microprocessor, data of said second rewritable program memory after rewrite operation on said second system bus which has been released; and

means for transferring, under control of said first microprocessor, the data after rewrite operation thus read onto said first system bus, thereby confirming correct rewrite operation by said first microprocessor.

7. An apparatus according to claim 4, wherein said second program memory is an electrically erasable read only memory.

8. A program rewriting apparatus comprising:

a first microprocessor system including a first microprocessor, a first rewritable memory for storing a program and a first system bus connected to said first microprocessor and said first rewritable memory, said first microprocessor reading out the program stored in said first rewritable memory through said first system bus to execute the program read out;

a second microprocessor system including a second microprocessor, a second rewritable memory for storing a program and a second system bus connected to said second microprocessor and said second rewritable memory, said second system bus being separate from said first system bus, and said second microprocessor reading out the program stored in said second rewritable memory through said second system bus to execute the program read out from said second rewritable memory, independently of execution by said first microprocessor;

a common memory provided to be accessible commonly to said first and second microprocessor systems under control of said first and second microprocessor systems; and

a controller connected to said first and second microprocessor systems and responsive to a request from a microprocessor of one microprocessor system, for causing a microprocessor of the other microprocessor system to release a system bus of said the other microprocessor system, so that the microprocessor of said one microprocessor system rewrites contents of a rewritable memory of the other microprocessor system using an update program stored in said common memory.

9. An apparatus according to claim 8, wherein said controller comprises:

means for assigning an address on a system bus of the other microprocessor system, in accordance with execution by a microprocessor of said one microprocessor system;

means for assigning data on a system bus of the other microprocessor system in accordance with execution by the microprocessor of said one microprocessor system, said data being read out from said common memory; and

means for writing data on the system bus of the other microprocessor system in a rewritable memory of the other microprocessor system, under control of the microprocessor of said one microprocessor system.

10. An apparatus according to claim 9, wherein said controller further comprises:

means for transferring data on the system bus of the other microprocessor system read out after rewriting operation from a rewritable memory of the other microprocessor system to a system bus of said one microprocessor system, in accordance with execution by the microprocessor of said one microprocessor system, so that the microprocessor of said one microprocessor system checks data after rewriting operation stored in the rewritable memory of the other microprocessor system.

11. An apparatus according to claim 8, wherein said rewritable memories include an electrically erasable read only memory.

12. An apparatus according to claim 8, wherein in an ordinary state, said first microprocessor controls data read/write operation of a disk drive and said second microprocessor controls driving operation of heads in said disk drive.

13. A disk device comprising:

a first microprocessor system for controlling data read/write operation of a disk drive, said first microprocessor system including a first microprocessor, a first rewritable memory for storing a program and a first system bus connected with said first microprocessor and said first rewritable memory, said first microprocessor reading out the program stored in said first rewritable memory through said first system bus to execute the program read out;

a second microprocessor system for controlling driving operation of heads in said disk drive, said second microprocessor system including a second microprocessor, a second rewritable memory for storing a program and a second system bus connected with said second microprocessor rand said second rewritable memory, said second system bus being separate from said first system bus, and said second microprocessor reading out the program stored in said second rewritable memory through said second system bus to execute the program read out from said second rewritable memory, independently of execution by said first microprocessor;

a common memory provided to be accessible commonly to said first and second microprocessor systems under control of said first and second microprocessor systems; and

a controller connected with said first and second microprocessor systems and responsive to a request from a microprocessor of one microprocessor system, for causing a microprocessor of the other microprocessor system to release a system bus of said other microprocessor system, so that the microprocessor of said one microprocessor system rewrites contents of a rewritable memory of said other microprocessor system using an update program stored in said common memory.

14. A disk device according to claim 13, wherein said controller comprises:

means for assigning an address on a system bus of said other microprocessor system, under control of a microprocessor of said one microprocessor system;

means for assigning data on a system bus of said the other microprocessor system, under control of the microprocessor of said one microprocessor system, said data being read out from said common memory; and

means for writing data on the system bus of said the other microprocessor system in a rewritable memory of said other microprocessor system under control of the microprocessor of said one microprocessor system.

15. A disk device according to claim 14, wherein said controller further comprises:

means for transferring data on the system bus of said other microprocessor system read out after rewriting operation from a rewritable memory of said other microprocessor system to a system bus of said one microprocessor system, under control of the microprocessor of said one microprocessor system, so that the microprocessor of said one microprocessor system checks data after rewriting operation stored in the rewritable memory of said other microprocessor system.

16. A disk device according to claim 13, wherein said rewritable memories include an electrically erasable read only memory.