Method for minimizing the hot carrier effect in N-MOSFET devices

• US 5,750,435 A
• Filed: 07/14/1997
• Issued: 05/12/1998
• Est. Priority Date: 07/26/1995
• Status: Expired due to Term

• Current Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Original Assignee: Chartered Semiconductor Manufacturing Incorporated (Mamoura Diversified Global Holding PJSC)
• Inventors: Pan, Yang
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): GURLEY, LYNNE ANN
• Application Number:
  US08/892,336
• Time in Patent Office: 302 Days
• Field of Search: 437/24, 437/35, 437/28, 437/29, 438/525, 438/528
• US Class Current: 438/525
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/28176 with a treatment, e.g. annealing, after the formation of the definitive gate conductor
• CPC Class Codes: H01L 29/512 the variation being parallel to the channel plane
• CPC Class Codes: H01L 29/518 the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET

Abstract

An N-Channel Metal Oxide Semiconductor Field Effect Transistor (N-MOSFET) with minimum susceptibility to the Hot Carrier Effect (HCE) and a method by which the N-MOSFET is fabricated. Formed upon a semiconductor substrate is a N-MOSFET structure including a gate oxide upon a semiconductor substrate, a gate electrode upon the gate oxide and a pair of N+ source/drain regions adjoining the gate electrode and the gate oxide. Implanted into the gate oxide regions beneath the gate electrode edges is a dose of a hardening ion. The hardening ion may be either nitrogen ion or fluorine ion. The hardening ion is implanted at an angle non-orthogonal to the plane of the semiconductor substrate through means of a large tilt angle ion implant process. Optionally, a Lightly Doped Drain (LDD) source/drain electrode structure or Double Doped Drain (DDD) source/drain electrode structure may be incorporated into the N-MOSFET structure.

Claims

1. A method for minimizing the Hot Carrier Effect (HCE) within N-Channel Metal Oxide Semiconductor Field Effect Transistors (N-MOSFETs) comprising:

forming upon a semiconductor substrate a field effect transistor structure comprising a gate oxide, a gate electrode formed upon the gate oxide and a pair of N+ source/drain regions formed within the semiconductor substrate;

implanting into the gate oxide regions beneath the gate electrode edges a dose of a hardening ion, the hardening ion comprising fluorine only, the dose of the hardening ion being implanted at a tilt angle non-orthogonal to the plane of the semiconductor substrate, the dose of the hardening ion being implanted through means of a large tilt angle ion implant process, the dose of the hardening ion being sufficient to provide an increased threshold for formation of interface states due to charge carriers injected from the semiconductor substrate into the gate oxide; and

annealing the semiconductor substrate.

2. The method of claim 1 wherein the gate oxide thickness is about 20 to about 200 angstroms.

3. The method of claim 2 wherein the tilt angle is about 7 to about 60 degrees from an axis orthogonal to the plane of the semiconductor substrate.

4. The method of claim 1 wherein the dose of the hardening ion is implanted at an ion implantation dose of about 1E14 to about 1E16 ions per square centimeter and an ion implantation energy of about 5 to about 50 keV.

5. The method of claim 1 wherein the semiconductor substrate is annealed at a temperature of about 800 to about 950 degrees centigrade for a time period of about 5 to about 100 minutes.

6. The method of claim 1 further comprising forming a Lightly Doped Drain source/drain region structure within the semiconductor substrate adjoining the gate electrode.

7. The method of claim 1 further comprising forming a Double Doped Drain (DDD) source/drain region structure within the semiconductor substrate adjoining the gate electrode.