Polysilicon pillar diode for use in a non-volatile memory cell

• US 5,751,012 A
• Filed: 06/07/1995
• Issued: 05/12/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Ireland, Philip J., Wolstenholme, Graham R.
• Primary Examiner(s): Wallace, Valencia Martin
• Application Number:
  US08/474,028
• Time in Patent Office: 1,070 Days
• Field of Search: 257/2, 257/3, 257/4, 257/530, 257/209, 257/37, 257/5, 365/163
• US Class Current: 257/5
• CPC Class Codes: H01L 29/8615 Hi-lo semiconductor devices, e.g. memory devices
• CPC Class Codes: H10B 63/10 Phase change RAM [PCRAM, PRAM] devices
• CPC Class Codes: H10B 63/20 comprising selection components having two electrodes, e.g. diodes

Abstract

There is described a memory cell having a vertically oriented polysilicon pillar diode for use in delivering large current flow through a variable resistance material memory element. The pillar diode comprises a plurality of polysilicon layers disposed in a vertical stack between a wordline and digitline. The memory element is disposed in series with the diode, also between the wordline and the digitline. The diode is capable of delivering the large current flow required to program the memory element without also requiring the surface space on the upper surface of the memory matrix normally associated with such powerful diodes. The invention allows memory cells to be disposed every 0.7 microns or less across the face of a memory matrix. Further, the memory cell is easily fabricated using standard processing techniques. The unique layout of the inventive memory cell allows fabrication with as few as three mask steps or less.

Claims

1. A memory cell having a first and second nodes, said cell comprising:

a memory element having a layer of programmable resistive material bounded by a first electrode and a second electrode, said memory element electrically coupled to said first node; and

a diode formed by depositing at least three silicon layers on a substrate and by selectively etching through said silicon layers to form a distinct pillar of silicon layers, said diode being electrically coupled to said memory element and to said second node, and said silicon layers comprising an N- layer, an N+ layer, and a P+ layer.

2. The memory cell of claim 1, wherein said programmable resistive material is chalcogenide.

3. The memory cell of claim 1, wherein said pillar is disposed above said first node, and wherein said memory element is disposed above said pillar, and wherein said second node is disposed above said memory element.

4. The memory cell of claim 1, wherein said first node is disposed in an oxide base and wherein said pillar is disposed on said oxide base.

5. The memory cell of claim 1, wherein said diode further comprises at least one layer of material that reduces the resistance of said diode in operation, said layer being formed during formation of said pillar.

6. The memory cell of claim 1, wherein said memory cell further comprises a shaping layer disposed between said layer of programmable resistive material and said pillar, said shaping layer contouring said layer of programmable resistive material to at least partially define an active area where said layer of programmable resistive material is in electrical contact with said diode.

7. The memory cell of claim 1, wherein said memory cell further comprises a cap layer disposed between said second node and said memory element, said cap layer contouring said second node to at least partially define a contact opening where said second node is in electrical contact with said memory element.

8. The memory cell of claim 1, wherein at least some of said silicon layers are polysilicon layers.

9. A memory matrix comprising:

a plurality of first address lines;

a plurality of second address lines;

a plurality of diodes being formed by depositing at least three silicon layers on a substrate and by selectively etching through said silicon layers to form a plurality of pillars of silicon layers, wherein each of said pillars forms a diode, wherein said silicon layers comprise an N- layer an N+ layer, and a P+ layer, and wherein each of said plurality of pillars has a first end and a second end, the first end of each of said plurality of pillars being coupled to a respective one of said plurality of first address lines; and

a plurality of memory elements, each of said plurality of memory elements having a first electrode coupled to said second end of a respective one of said plurality of pillars, a second electrode coupled to a respective one of said plurality of second address lines, and a layer of programmable resistive material coupled between said first electrode and said second electrode.

10. The matrix of claim 9, wherein said plurality of first address lines contain tungsten.

11. The matrix of claim 10, wherein said plurality of first address lines are disposed in a plurality of trenches recessed in an oxide base.

12. The matrix of claim 11, wherein said plurality of trenches are coated with a layer material effective to lower electrical resistance experienced by said first address lines during operation.

13. The matrix of claim 9, wherein each of said plurality of diodes is disposed above a respective first address line, and wherein each memory element is disposed above a respective diode, and wherein each of said plurality of second address lines is disposed above a respective memory element.

14. The memory matrix of claim 9, wherein each of said plurality of diodes further comprises at least one layer effective to reduce electrical resistance experienced by said diode during operation.

15. The memory matrix of claim 9, further comprising a shaping layer disposed between each of said plurality of diodes and said respective layer of programmable resistive material, said shaping layer contouring said layer of programmable resistive material to define an active area.

16. The memory matrix of claim 15, wherein said shaping layer is a nitride layer.

17. The memory matrix of claim 9, further comprising a cap layer disposed between each of said plurality of memory elements and said respective second address line, said cap layer contouring said second address line to define an active area.

18. The memory matrix of claim 15, wherein said cap layer is a nitride layer.

19. A memory cell comprising:

a memory element having a first electrode and a second electrode, and having a layer of programmable resistive material being electrically coupled to said first electrode and to said second electrode; and

a diode being formed by a pillar comprised of at least three silicon layers being disposed on a substrate, said silicon layers comprising an N- layer, an N+ layer, and a P+ layer, and said diode being electrically coupled to said memory element.

20. A memory matrix comprising:

a plurality of first address lines;

a plurality of second address lines;

a plurality of diodes, each of said plurality of diodes being formed by a pillar comprised of at least three silicon layers, wherein said silicon layers comprise an N- layer, an N+ layer, and a P+ layer; and

a plurality of memory elements, each of said plurality of memory elements having a layer of resistive material being electrically coupled to a respective one of said plurality of diodes.

21. A memory cell having a first and second nodes, said cell comprising:

a memory element having a layer of programmable resistive material bounded by a first electrode and a second electrode, said memory element electrically coupled to said first node; and

a diode formed by depositing at least three silicon layers and a TiN layer on a substrate and by selectively etching through said silicon layers and said TiN layer to form a distinct pillar, said diode being electrically coupled to said memory element and to said second node.

22. A memory matrix comprising:

a plurality of first address lines being disposed in a plurality of trenches recessed in a dielectric base, said plurality of trenches being coated with a layer of TiN;

a plurality of second address lines;

a plurality of diodes being formed by depositing at least three silicon layers on a substrate and by selectively etching through said silicon layers to form a plurality of pillars of silicon layers, wherein each of said pillars forms a diode, and wherein each of said plurality of pillars has a first end and a second end, the first end of each of said plurality of pillars being coupled to a respective one of said plurality of first address lines; and

a plurality of memory elements, each of said plurality of memory elements having a first electrode coupled to said second end of a respective one of said plurality of pillars, a second electrode coupled to a respective one of said plurality of second address lines, and a layer of programmable resistive material coupled between said first electrode and said second electrode.

23. A memory cell comprising:

a memory element having a first electrode and a second electrode and having a layer of programmable resistive material coupled to said first electrode and said second electrode; and

a diode coupled to said memory element and formed by a distinct pillar comprising a plurality of silicon layers and a layer of TiN.

24. A memory matrix comprising:

a plurality of first address lines;

a plurality of second address lines;

a plurality of diodes being formed by depositing on a substrate a plurality of silicon layers and a layer of TiN and by selectively etching through said plurality of silicon layers to form a plurality of pillars of silicon layers, wherein each of said plurality of pillars forms a diode, and wherein each of said plurality of pillars has a first end and a second end, the first end of each of said plurality of pillars being coupled to a respective one of said plurality of first address lines; and

a plurality of memory elements, each of said plurality of memory elements having a first electrode coupled to said second end of a respective one of said plurality of pillars, a second electrode coupled to a respective one of said plurality of second address lines, and a layer of resistive material coupled to said first electrode and to said second electrode.