Semiconductor reliability test chip

• US 5,751,015 A
• Filed: 11/17/1995
• Issued: 05/12/1998
• Est. Priority Date: 11/17/1995
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Gonzalez, Fernando, Corbett, Tim J., Scholer, Raymond P.
• Primary Examiner(s): Crane, Sara W.
• Assistant Examiner(s): WILLIAMS, ALEXANDER O
• Application Number:
  US08/560,544
• Time in Patent Office: 907 Days
• Field of Search: 257/48, 257/620, 257/203, 257/207, 257/208, 257/210, 257/778, 257/211
• US Class Current: 257/48
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G01R 31/3163 Functional testing
• CPC Class Codes: H01L 22/34 Circuits for electrically characterising or monitoring manufacturing processes, e. g. whole test die, wafers filled with test structures, on-board-devices incorporated on each die, process control monitors or pad structures thereof, devices in scribe line switching, multiplexing, gating devices G01R19/25; process control with lithography, e.g. dose control, G03F7/20; structures for alignment control by optical means G03F7/70633
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48463 the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01327 Intermediate phases, i.e. intermetallics compounds
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

A semiconductor test chip including a plurality of test functions. The test functions of the semiconductor test chip include bond pad pitch and size effects on chip design, wire bond placement accuracy regarding placement of the wire bond on the bond pad, evaluation of bond pad damage (cratering) effect on the area of the chip below the bond pad during bonding of the wire on the bond pad, street width effects regarding the use of thinner saw cuts in cutting the individual chips from the wafer, thermal impedance effects for thermal testing capabilities, ion mobility evaluation capabilities and chip on board in flip chip application test capabilities.

Claims

1. A semiconductor test chip having a scribe area around the periphery thereof for simulating various conditions as a result of the manufacture, packaging, and use of a semiconductor chip, said test chip comprising:

a chip including a periphery formed by at least four sides and a plurality of contact pads located substantially adjacent a portion of the periphery of the chip, a portion of the plurality of contact pads being located in a first row and a second row located substantially behind the first row on a portion of at least one side of the chip; and

a plurality of thin gate and thick gate transistor devices for the measurement of the temperature of the chip.

2. The semiconductor test chip of claim 1, wherein the plurality of contact pads are located in at least two rows substantially adjacent the periphery of the chip on a portion of the periphery of the at least one side of the chip.

3. The semiconductor test chip of claim 1, wherein the plurality of contact pads are of at least two different geometric shapes.

4. The semiconductor test chip of claim 1, wherein at least two of the contact pads of the plurality of contact pads differ in size.

5. The semiconductor test chip of claim 1, wherein the plurality of contact pads includes contact pads having different pitches of mounting on the chip.

6. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

at least one line located substantially in the scribe area of the chip extending about a portion of the periphery of the chip.

7. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe of the chip extending substantially throughout the periphery of the chip.

8. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe area of the chip extending throughout a portion thereof, at least two of the lines of the plurality of lines having a width which differs from another.

9. The semiconductor chip of claim 1, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe area of the chip extending throughout a portion thereof, each line of the plurality of lines having a spacing which differs from another line of the plurality of lines.

10. The semiconductor chip of claim 1, wherein the plurality of contact pads are formed in a plurality of groups of contact pads, each group of pads extending substantially about one side of the periphery of the chip.

11. The semiconductor chip of claim 1, wherein the plurality of contact pads are formed in a plurality of groups of contact pads extending substantially about the periphery of the chip, each individual group of contact pads being of different size than another group of contact pads of the plurality of contact pads.

12. The semiconductor chip of claim 1, wherein the plurality of contact pads are formed in a plurality of groups of contact pads extending substantially about the a portion of the periphery of the chip, each group of the plurality of groups of contacts including at least a first row of contacts and at least a second row of contacts located adjacent the first row of contacts.

13. The semiconductor chip of claim 1, wherein the chip further includes:

a polysilicon area located under a portion of the plurality of contact pads.

14. The semiconductor chip of claim 1, wherein the chip further includes:

an area of polysilicon located under a portion of the plurality of contact pads, the area of polysilicon having at least two differing configurations.

15. The semiconductor chip of claim 1, wherein the chip further includes:

a plurality of resistive type heaters located on a portion of the chip.

16. The semiconductor chip of claim 14, wherein each resistive type heater of the plurality of heaters is independently connected to a connector pad on the chip.

17. The semiconductor chip of claim 1, wherein the semiconductor chip further includes:

a plurality of transistors to measure any temperature gradient in the chip.

19. The semiconductor test chip of claim 1, wherein the chip is substantially square in shape.

20. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located substantially in the center portion of the chip.

21. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of flip chip test pads in an array located in substantially the center portion of the chip.

22. The semiconductor test chip of claim 1, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located substantially the center of the chip, a portion of the plurality of flip chip test pads being connected in a daisy chain connection by conductors extending therebetween, the portion of the plurality of flip chip test pads being connected in a daisy chain being independent of other pads of the plurality of flip chip test pads.

48. The semiconductor chip of claim 1, wherein the semiconductor chip further includes:

a plurality of transistors to measure any temperature gradient in the chip.

18. A semiconductor test chip having a scribe area around the periphery thereof for simulating various conditions as a result of the manufacture, packaging, and use of a semiconductor chip, said test chip comprising:

a chip including a periphery formed by at least four sides and a plurality of contact pads located substantially adjacent a portion of the periphery of the chip, a portion of the plurality of contact pads being located in a first row and a second row located substantially behind the first row on a portion of at least one side of the chip; and

a plurality of thin gate and thick gate transistor devices for the measurement of the ion contamination of the chip.

23. A semiconductor test chip for simulating various conditions of the manufacture, packaging, and use of a semiconductor chip, said semiconductor test chip having a scribe area located about the periphery thereof, said semiconductor test chip including:

a chip including a periphery having at least four sides, a plurality of contact pads located on a portion of the periphery, and a line formed in the scribe area of the periphery of the chip; and

at least one thin gate transistor and/or thick gate transistor capable of responding to temperature increases in portions of the chip.

24. The semiconductor test chip of claim 23, wherein the semiconductor chip further includes:

at least one resistance heater therein.

25. The semiconductor test chip of claim 23 wherein the semiconductor test chip further includes:

an area of polysilicon extending beneath at least a portion of the contact pads located on the chip.

26. The semiconductor test chip of claim 23, wherein the semiconductor test chip further includes:

at least one transistor capable of responding to temperature increases.

28. The semiconductor test chip of claim 23, wherein the semiconductor test chip further includes:

at least two flip chip test pads located thereon.

29. The semiconductor test chip of claim 23, wherein the semiconductor test chip further includes:

at least two flip chip test pads located thereon being interconnected.

30. The semiconductor test chip of claim 23, wherein the semiconductor test chip includes a plurality of contact pads, the contact pads being arranged in groups of pads, each group of pads being arranged in two rows about a portion of the periphery of the chip.

31. The semiconductor test chip of claim 30, wherein one row of contact pads of each contact pad of each group of contact pads contains at least a portion of a layer of polysilicon located thereunder.

27. A semiconductor test chip having a scribe area around the periphery thereof for simulating various conditions of the manufacture, packaging, and use of a semiconductor chip, said semiconductor test chip having a scribe area located about the periphery thereof, said semiconductor test chip including;

a chip including a periphery having at least four sides, a plurality of contact pads located on a portion of the periphery, and a line formed in the scribe area of the periphery of the chip; and

at least one thin gate transistor and/or thick gate transistor capable of responding to ion mobility in portions of the chip.

32. A semiconductor chip comprising:

a chip having a periphery formed by at least four sides and a plurality of contact pads located substantially adjacent a portion of the periphery of the chip, a portion of the plurality of contact pads having active circuitry of the chip thereunder and a layer of insulating material located between the portion of the plurality of contact pads and the active circuitry of the ship; and

a plurality of thin gate and thick gate transistor devices for the measurement of the temperature of the chip.

33. The semiconductor test chip of claim 32, wherein the plurality of contact pads are located in at least two rows substantially adjacent the periphery of the chip on a portion of the periphery of the at least one side of the chip.

34. The semiconductor test chip of claim 32, wherein the plurality of contact pads are of at least two different geometric shapes.

35. The semiconductor test chip of claim 32, wherein at least two of the contact pads of the plurality of contact pads differ in size.

36. The semiconductor test chip of claim 32, wherein the plurality of contact pads includes contact pads having different pitches of mounting on the chip.

37. The semiconductor test chip of claim 32, wherein the semiconductor chip further includes:

at least one line located substantially in the scribe area of the chip extending about a portion of the periphery of the chip.

38. The semiconductor test chip of claim 32, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe of the chip extending substantially throughout the periphery of the chip.

39. The semiconductor test chip of claim 32, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe area of the chip extending throughout a portion thereof, at least two of the lines of the plurality of lines having a width which differs from another.

40. The semiconductor chip of claim 32, wherein the semiconductor chip further includes:

a plurality of lines located substantially in the scribe area of the chip extending throughout a portion thereof, each line of the plurality of lines having a spacing which differs from another line of the plurality of lines.

41. The semiconductor chip of claim 32, wherein the plurality of contact pads are formed in a plurality of groups of contact pads, each group of pads extending substantially about one side of the periphery of the chip.

42. The semiconductor chip of claim 32, wherein the plurality of contact pads are formed in a plurality of groups of contact pads extending substantially about the periphery of the chip, each individual group of contact pads being of different size than another group of contact pads of the plurality of contact pads.

43. The semiconductor chip of claim 32, wherein the plurality of contact pads are formed in a plurality of groups of contact pads extending substantially about the a portion of the periphery of the chip, each group of the plurality of groups of contacts including at least a first row of contacts and at least a second row of contacts located adjacent the first row of contacts.

44. The semiconductor chip of claim 32, wherein the chip further includes:

a polysilicon area located under at least a portion of the plurality of contact pads.

45. The semiconductor chip of claim 33, wherein the chip further includes:

an area of polysilicon located under a portion of the plurality of contact pads, the area of polysilicon having at least two differing configurations.

46. The semiconductor chip of claim 32, wherein the chip further includes:

a plurality of resistive type heaters located on a portion of the chip.

47. The semiconductor chip of claim 46, wherein each resistive type heater of the plurality of heaters is independently connected to a connector pad on the chip.

49. The semiconductor test chip of claim 32, wherein the chip is substantially square in shape.

50. The semiconductor test chip of claim 32, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located substantially in the center portion of the chip.

51. The semiconductor test chip of claim 32, wherein the semiconductor chip further includes:

a plurality of flip chip test pads in an array located in substantially the center portion of the chip.

52. The semiconductor test chip of claim 32, wherein the semiconductor chip further includes:

a plurality of flip chip test pads located substantially the center of the chip, a portion of the plurality of flip chip test pads being connected in a daisy chain connection by conductors extending therebetween, the portion of the plurality of flip chip test pads being connected in a daisy chain being independent of other pads of the plurality of flip chip test pads.