Insulated gate semiconductor device

• US 5,751,024 A
• Filed: 11/28/1995
• Issued: 05/12/1998
• Est. Priority Date: 03/14/1995
• Status: Expired due to Term

• Current Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Original Assignee: Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Takahashi, Hideki
• Primary Examiner(s): Loke, Steven H.
• Application Number:
  US08/566,572
• Time in Patent Office: 896 Days
• Field of Search: 257/133, 257/139, 257/143, 257/147, 257/149, 257/155, 257/172, 257/339, 257/341, 257/342, 257/330, 257/329, 257/331, 257/332
• US Class Current: 257/139
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT

Abstract

It is an object to obtain an insulated gate semiconductor device with an unreduced current value capable of being turned off while adopting structure for reducing the ON voltage, and a manufacturing method thereof. An N layer (43) is provided in close contact on a surface of an N^- layer (42), a P base layer (44) is provided in close contact on the surface of the N layer (43), and a trench (47) which passes at least through the P base layer (44) is provided, and a gate electrode (49) is provided in the trench (47) through a gate insulating film (48). The carrier distribution of the N^- layer (42) becomes closer to the carrier distribution of a diode, and an ON voltage is decreased and a current value capable of being turned off is not decreased when turning off. Accordingly, there are provided an insulated gate semiconductor device with low power consumption, small size, large capacity and high reliability.

Claims

1. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type having first and second main surfaces;

a second semiconductor layer of a second conductivity type with a low impurity concentration provided on the first main surface of said first semiconductor layer;

a third semiconductor layer of the second conductivity type with an impurity concentration higher than the impurity concentration of said second semiconductor layer and provided in close contact on a surface of said second semiconductor layer;

a fourth semiconductor layer of the first conductivity type provided in close contact on a surface of said third semiconductor layer;

a fifth semiconductor layer of the second type selectively provided in a surface of said fourth semiconductor layer;

a trench having an opening in a surface of said fifth semiconductor layer and having a depth extending through at least said fourth semiconductor layer from the surface of said fifth semiconductor layer;

an insulating film provided on an entire inner wall of said trench;

a control electrode provided in said trench, facing said fourth semiconductor layer through said insulating film;

a first main electrode provided on the surface of said fourth and fifth semiconductor layers; and

a second main electrode provided on the second main surface of said first semiconductor layer wherein said second semiconductor layer is thicker than said third semiconductor layer.

2. The insulated gate semiconductor device according to claim 1, wherein said trench has a depth which extends also through said third semiconductor layer to reach said second semiconductor layer.

3. The insulated gate semiconductor device according to claim 1, wherein said trench has a depth which extends into said third semiconductor layer but does not reach a boundary between said second semiconductor layer and said third semiconductor layer.

4. The insulted gate semiconductor device according to claim 3, wherein a thickness of said third semiconductor layer between a bottom of said trench and said second semiconductor layer is not more than a critical thickness at which a rapid decrease appears in a breakdown voltage of said insulated gate semiconductor device with an increase in the thickness.

5. The insulated gate semiconductor device according to claim 1, wherein said second semiconductor layer extends through said first semiconductor layer and is partially exposed in the second main surface of said first semiconductor layer.

6. The insulated gate semiconductor device according to claim 1, wherein a sixth semiconductor layer of the second conductivity type with an impurity concentration higher than the impurity concentration of said second semiconductor layer is provided between said first semiconductor layer and said second semiconductor layer.

7. The insulated gate semiconductor device according to claim 6, wherein said sixth semiconductor layer extends through said first semiconductor layer and is partially exposed in the second main surface of said first semiconductor layer.

8. The insulated gate semiconductor device according to claim 1, wherein said trench includes a plurality of unit trenches arranged side by side, and a part of the exposed surface of said fourth semiconductor layer is provided being interposed between said unit trenches adjacent each other.

9. The insulated gate semiconductor device according to claim 8, wherein the exposed surface of said fourth semiconductor layer is divided into a plurality of unit exposed surfaces by a part of said fifth semiconductor layer, the plurality of unit exposed surfaces being arranged alternately with part of said fifth semiconductor layer along said trench.

10. The insulated gate semiconductor device according to claim 1, wherein said trench is filled uniformly with said control electrode from a bottom wall substantially to a top opening thereof.

11. An insulated gate semiconductor device, comprising:

a first semiconductor layer of a first conductivity type having first and second main surfaces;

a second semiconductor layer of a second conductivity type with a low impurity concentration provided on the first main surface of said first semiconductor layer;

a third semiconductor layer of the second conductivity type with an impurity concentration higher than the impurity concentration of said second semiconductor layer and provided in close contact on a surface of said second semiconductor layer;

a fourth semiconductor layer of the first conductivity type provided in close contact on a surface of said third semiconductor layer;

a fifth semiconductor layer of the second type selectively provided in a surface of said fourth semiconductor layer;

a trench having an opening in a surface of said fifth semiconductor layer and having a depth extending through at least said fourth semiconductor layer from the surface of said fifth semiconductor layer;

an insulating film provided on an inner wall of said trench;

a control electrode provided in said trench, facing said fourth semiconductor layer through said insulating film;

a first main electrode provided on the surface of said fourth and fifth semiconductor layers, said first main electrode not contacting any other semiconductor layer than said fourth and fifth semiconductor layers; and

a second main electrode provided on the second main surface of said first semiconductor layer wherein said second semiconductor layer is thicker than said third semiconductor layer.