Electrically erasable and programmable read only memory (EEPROM) having multiple overlapping metallization layers

• US 5,751,038 A
• Filed: 11/26/1996
• Issued: 05/12/1998
• Est. Priority Date: 11/26/1996
• Status: Expired due to Term

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: Philips Electronics North America Corporation (Koninklijke Philips N.V.)
• Inventors: Mukherjee, Satyendranath
• Primary Examiner(s): Munson, Gene M.
• Application Number:
  US08/753,554
• Time in Patent Office: 532 Days
• Field of Search: 257/316, 257/390, 257/618, 365/104, 365/185.01, 365/185.05
• US Class Current: 257/316
• CPC Class Codes: H10B 41/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

An electrically erasable and programmable read only memory (EEPROM) includes an array of trench memory cells, with each memory cell having a semiconductor drain region adjacent a surface-adjoining portion of the trench. The EEPROM is provided with at least two overlapping metallization layers overlying the memory cells and separated from each other and from the trenches and the drain regions by regions of insulating material. The overlapping metallization layers contact the drain regions of the underlying memory cells through the insulating material. This configuration results in a memory array having a very high packing density.

Claims

1. An Electrically Erasable and Programmable Read Only Memory (EEPROM) having an array of memory cells, each memory cell having a trench configuration and a semiconductor drain region adjacent a surface-adjoining portion of said trench, characterized in that said EEPROM is provided with at least two overlapping metallization layers overlying said memory cells separated from each other and from said trenches and said drain regions by regions of insulating material, and in that each of said overlapping metallization layers contact the drain region of at least one underlying memory cell through said insulating material.

2. An EEPROM as in claim 1, wherein a single semiconductor layer is provided as the drain regions for a plurality of memory cells in a single column.

3. An EEPROM as in claim 2, wherein each of said overlapping metallization layers contacts an underlying semiconductor layer, with each semiconductor layer forming the drain region for a plurality of memory cells in a single column.

4. An EEPROM as in claim 3, wherein each metallization layer contacts the underlying semiconductor layer beneath said metallization layer through said insulating material at a number of contact locations which is less than the number of memory cells in the single column.

5. An EEPROM as in claim 4, wherein the number of memory cells is 8 times larger than the number of contact locations.

6. An EEPROM as in claim 4, wherein the number of memory cells is 16 times larger than the number of contact locations.

7. An EEPROM as in claim 4, wherein the number of memory cells is 32 times larger than the number of contact locations.

8. An EEPROM as in claim 1, wherein said at least two overlapping metallization layers are provided with staggered electrical contacts.