System and method for accelerated occlusion culling
First Claim
1. An occlusion culling circuit for use in a graphics computer, comprising:
- a central processor;
a depth comparison circuit for receiving a graphics primitive from said central processor and for comparing an incoming depth value for each address in said graphics primitive with a current depth value for a rendered pixel at a corresponding address, said depth comparison circuit generating a result signal having a first logical value when said incoming depth value passes a depth comparison function and a second logical value when said incoming depth value fails said depth comparison function;
a logic circuit for receiving said result signal of said depth comparison circuit and for generating a depth compare signal, said logic circuit latching said depth compare signal at said first logical value upon receipt of said result signal having said first logical value;
a depth buffer for storing depth values of said graphics primitive;
a color buffer for storing color values of said graphics primitive; and
wherein said central processor stores said color values in said color buffer and said depth values in said depth buffer when said logic circuit latches said first logical value for said graphics primitive.
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Accused Products
Abstract
An occlusion culling circuit for use in a graphics computer receives graphics primitives data including x and y coordinates for each pixel, a z depth value, and r, g, b, and a or index color data. For each group of primitives, the graphics computer scans the primitive and determines a volume which completely bounds the primitive. The z depth values for the pixels comprising the bounding volume are then compared by the occlusion culling circuit to the depths of the pixels in the already rendered primitives to determine whether any pixels in the incoming primitive are visible. If no pixels are visible, the occlusion culling circuit clears the result register and receives the next graphics primitive. If, on the other hand, one or more pixels is visible, the occlusion culling circuit completely renders the primitives bounded by the bounding volume. Since the graphics primitives which are totally occluded can bypass the more intensive pixel by pixel processing and storage, the speed and efficiency of the graphics computer can be significantly increased.
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Citations
18 Claims
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1. An occlusion culling circuit for use in a graphics computer, comprising:
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a central processor; a depth comparison circuit for receiving a graphics primitive from said central processor and for comparing an incoming depth value for each address in said graphics primitive with a current depth value for a rendered pixel at a corresponding address, said depth comparison circuit generating a result signal having a first logical value when said incoming depth value passes a depth comparison function and a second logical value when said incoming depth value fails said depth comparison function; a logic circuit for receiving said result signal of said depth comparison circuit and for generating a depth compare signal, said logic circuit latching said depth compare signal at said first logical value upon receipt of said result signal having said first logical value; a depth buffer for storing depth values of said graphics primitive; a color buffer for storing color values of said graphics primitive; and wherein said central processor stores said color values in said color buffer and said depth values in said depth buffer when said logic circuit latches said first logical value for said graphics primitive. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method for accelerated occlusion culling in a graphics computer, comprising the steps of:
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receiving data associated with each pixel in a graphics primitive; performing a depth comparison function by comparing an depth value of one said pixel in said graphics primitive with a current depth value for a rendered pixel at a corresponding address; generating a result signal having a having a first logical value when said depth value passes said depth comparison function and a second logical value when said depth value fails said depth comparison function; latching said result signal in a depth compare result register so that said first value remains in said depth compare result register after a first occurrence of said result signal having a first logic value; reading said depth compare result register to determine if said first logic value was latched in said depth compare result register; and storing color data values of said graphics primitive in a color buffer and depth data values of said graphics primitive in a depth buffer when said first logic value is read from said depth compare result register. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. An occlusion culling circuit for use in a graphics computer, comprising:
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depth comparison means for receiving a bounded volume for a graphics primitive and for comparing a depth value for each pixel in said graphics primitive with a current depth value for a rendered pixel at a corresponding address, said depth comparison circuit generating a result signal having a first logical value when said incoming depth value passes a depth comparison function and a second logical value when said incoming depth value fails said depth comparison function; latching means for receiving said result signal of said depth comparison means and for generating a depth compare signal, said logic circuit latching said depth compare signal at said first logical value upon receipt of said result signal having said first logical value; depth buffer means for storing depth values of said graphics primitive; color buffer means for storing color values of said graphics primitive; and wherein said central processor stores said color values in said color buffer and said depth values in said depth buffer when said logic circuit latches said first logical value for said graphics primitive.
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Specification