Graphics accelerator chip and method
First Claim
Patent Images
1. A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor, the graphics accelerator chip comprising:
- (a) a host logic interface logically coupled to the microprocessor via the external data bus for transferring the instructions and data between the graphics accelerator chip and the microprocessor;
(b) a first-in first-out (FIFO) memory logically coupled to the host logic interface for receiving and buffering the instructions and data, wherein the FIFO memory address space is mapped onto a contiguous sequential address space of the microprocessor;
(c) a state machine logically coupled to the FIFO memory for receiving and interpreting the instructions and data, and performing logical state operations based upon the instructions and data;
(d) a temporary memory logically coupled to the state machine for temporarily storing a graphics instruction while the data associated with that graphics instruction is outputted from the FIFO memory; and
(e) a graphics register set logically coupled to the state machine and the temporary memory via a first internal data bus, wherein the graphics register set receives and interprets the graphics instruction and data and performs logical graphics operations based upon the graphics instruction and data.
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Abstract
A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor. A host logic interface buffers the information received from the microprocessor with an on-chip first-in first-out (FIFO) memory which has an address space mapped onto a contiguous sequential address space of the microprocessor. A state machine having a temporary memory receives and interprets instructions and data from the FIFO memory, and routes them to a graphics register set which performs logical graphics operations based upon the graphics instructions and data. The temporary memory stores the last primitive command received, allowing the chip to perform multiple graphics operations where a primitive command is received from the microprocessor only once. A separate data bus from the host logic interface to the graphics register set enables direct access to the graphics registers from the microprocessor.
114 Citations
29 Claims
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1. A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor, the graphics accelerator chip comprising:
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(a) a host logic interface logically coupled to the microprocessor via the external data bus for transferring the instructions and data between the graphics accelerator chip and the microprocessor; (b) a first-in first-out (FIFO) memory logically coupled to the host logic interface for receiving and buffering the instructions and data, wherein the FIFO memory address space is mapped onto a contiguous sequential address space of the microprocessor; (c) a state machine logically coupled to the FIFO memory for receiving and interpreting the instructions and data, and performing logical state operations based upon the instructions and data; (d) a temporary memory logically coupled to the state machine for temporarily storing a graphics instruction while the data associated with that graphics instruction is outputted from the FIFO memory; and (e) a graphics register set logically coupled to the state machine and the temporary memory via a first internal data bus, wherein the graphics register set receives and interprets the graphics instruction and data and performs logical graphics operations based upon the graphics instruction and data. - View Dependent Claims (2, 3, 4, 8, 10, 13, 15, 17, 19, 21, 23)
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5. A graphics accelerator chip which interprets instructions and data transferred from a microprocessor via an external data bus logically coupled to the microprocessor, the graphics accelerator chip comprising:
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(a) receive means for receiving a graphics instruction and for receiving a pixel signal representative of a portion of a display image; (b) transfer means logically coupled to the receive means for transferring the pixel signal representative of a portion of a display image to a display memory logically coupled to the graphics accelerator chip; (c) graphics register means logically coupled to the receive means and display memory for interpreting the graphics instruction and for performing a logical graphics operation upon the pixel signal representative of a portion of a display image; and (d) control means logically coupled to the graphics register means for instructing the graphics register means to perform a logical exclusive-or (XOR) copy of the pixel signal representative of a portion of a display image located at a first location within the display memory to a pixel signal representative of a portion of a display image located at a second location within the display memory, perform a logical XOR copy of the pixel signal representative of a portion of a display image located at the second location within the display memory to the pixel signal representative of a portion of a display image located at the first location within the display memory, and perform a logical XOR copy of the pixel signal representative of a portion of a display image located at the first location within the display memory to the pixel signal representative of a portion of a display image located at the second location within the display memory; wherein the pixel signal representative of a portion of a display image located at the first location within the display memory is exchanged with the pixel signal representative of a portion of a display image located at the second location within the display memory.
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6. A method of performing a pixel exchange operation with a graphics accelerator chip comprising the steps of:
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(a) receiving a graphics instruction and a pixel signal representative of a portion of a display image; (b) transferring the pixel signal representative of a portion of a display image to a display memory logically coupled to the graphics accelerator chip; (c) interpreting the graphics instruction and for performing a logical XOR copy of the pixel signal representative of a portion of a display image located at a first location within the display memory to a pixel signal representative of a portion of a display image located at a second location within the display memory; (d) performing a logical XOR copy of the pixel signal representative of a portion of a display image located at the second location within the display memory to the pixel signal representative of a portion of a display image located at the first location within the display memory; and (e) performing a logical XOR copy of the pixel signal representative of a portion of a display image located at the first location within the display memory to the pixel signal representative of a portion of a display image located at the second location within the display memory; wherein the pixel signal representative of a portion of a display image located at the first location within the display memory is exchanged with the pixel signal representative of a portion of a display image located at the second location within the display memory.
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7. A method of performing a draw string operation with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, and a display memory, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with a draw string primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) initializing a rectangular array of bitmap cells in the display memory, the bitmap cells addressable by cell row and cell column; (2) transferring the draw string primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (4) transferring a cell column value, a cell row value, and a cell width value from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory; (5) using the graphics accelerator chip to transfer pixels from a cell in the display memory corresponding to the cell column value and cell row value stored in FIFO memory to a destination location in the display memory, and move the destination location to the right by the value of the cell width value; and (6) returning to step (4) if there are cell column and row values which have not been transferred from the data processing system to the graphics accelerator chip; wherein the draw string primitive command is transferred from the data processing system to the graphics accelerator chip only once.
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9. A method of performing an ordered dither operation with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, and a display memory, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with a dither primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) initializing a table of matrix values; (2) transferring the dither primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a width value, and a height value; (4) performing a primary color addition operation to the color value of a pixel in the display memory located at (X,Y), the color value comprising an integer portion and a fractional portion; (5) computing a matrix value using the (X,Y) location as an index into the table of matrix values; (6) using the graphics accelerator chip to compare the matrix value to the fractional portion of the color value; and (7) if the matrix value is greater than the fractional portion of the color value, using the graphics accelerator chip to increment the integer portion of the color value; wherein the incrementing of the integer portion of the color value based upon the matrix value results in smooth shading.
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11. A method of performing multiple graphics operations with a graphics accelerator chip using a programmable data processing system having a data input device and a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with a primitive command and multiple data parameters for each of the multiple graphics operations to be performed; (b) using the programmable data processing system to perform the steps of; (1) transferring the primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (2) transferring the multiple data parameters corresponding to one of the multiple graphics operations from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory; (3) using the graphics accelerator chip to perform a graphics operation corresponding to the primitive command stored in the temporary memory and multiple data parameters stored in the FIFO memory; and (4) returning to step (2) if there are multiple data parameters which have not been transferred from the data processing system to the graphics accelerator chip; wherein the primitive command is transferred from the data processing system to the graphics accelerator chip only once.
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12. A method of horizontally flipping a rectangular bitmap within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with a flip primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) dividing the rectangular bitmap having a width W and a height H into a left half A and a right half B having equal widths; (2) transferring the flip primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (4) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-X,Y); (5) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-X,Y) to a pixel in A located at (X,Y); (6) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-X,Y); wherein X varies from 0 to int(W/2)-1 and Y varies from 0 to H, and wherein the pixels of A are exchanged with the pixels of B in the display memory.
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14. A method of vertically flipping a rectangular bitmap within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with a flip primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) dividing the rectangular bitmap having a width W and a height H into an upper half A and a lower half B having equal heights; (2) transferring the flip primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (4) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (X,H-Y); (5) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (X,H-Y) to a pixel in A located at (X,Y); (6) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (X,H-Y); wherein X varies from to W and Y varies from 0 to int(H/2)-1, and wherein the pixels of A are exchanged with the pixels of B in the display memory.
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16. A method of diagonally flipping a rectangular bitmap within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with a flip primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) dividing the rectangular bitmap having a width W and a height H into an upper triangle A and a lower triangle B having equal heights and widths; (2) transferring the flip primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (4) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (Y,X); (5) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (Y,X) to a pixel in A located at (X,Y); (6) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (Y,X); wherein X varies from 0 to W, Y varies from 0 to H, X is greater than Y, and wherein the pixels of A are exchanged with the pixels of B in the display memory.
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18. A method of rotating a rectangular bitmap by 180°
- within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of;
(a) using the data input device to provide the programmable data processing system with a rotate primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) dividing the rectangular bitmap having a width W and a height H into an upper half A and a lower half B having equal heights; (2) transferring the rotate primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (4) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-X,H-Y); (5) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-X,H-Y) to a pixel in A located at (X,Y); (6) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-X,H-Y); wherein X varies from 0 to W and Y varies from 0 to int(H/2)-1, and wherein the pixels of A are exchanged with the pixels of B in the display memory.
- within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of;
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20. A method of rotating a rectangular bitmap by 90°
- within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of;
(a) using the data input device to provide the programmable data processing system with a rotate primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) dividing the rectangular bitmap having an even width W and an even height H into an upper left quarter A, an upper right quarter B, a lower right quarter C, and a lower left quarter D having equal heights and widths; (2) transferring the rotate primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (4) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-Y,X); (5) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-Y,X) to a pixel in A located at (X,Y); (6) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-Y,X); (7) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-Y,X) to a pixel in C located at (W-X,H-Y); (8) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in C located at (W-X,H-Y) to a pixel in B located at (W-Y, X); (9) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-Y,X) to a pixel in C located at (W-X,H-Y); (10) for each pixel in C, using the graphics accelerator chip to perform a logical XOR copy of a pixel in C located at (W-X,H-Y) to a pixel in D located at (H-X,Y); (11) for each pixel in C, using the graphics accelerator chip to perform a logical XOR copy of a pixel in D located at (H-X,Y) to a pixel in C located at (W-X,H-Y); (12) for each pixel in C, using the graphics accelerator chip to perform a logical XOR copy of a pixel in C located at (W-X,H-Y) to a pixel in D located at (H-X,Y); wherein X varies from 0 to int(W/2)-1 and Y varies from 0 to int(H/2)-1 , and wherein the pixels of B are exchanged with the pixels of A, the pixels of C are exchanged with the pixels of B, the pixels of D are exchanged with the pixels of C, the pixels of A are exchanged with the pixels of D in the display memory.
- within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of;
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22. A method of rotating a rectangular bitmap by 90°
- within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of;
(a) using the data input device to provide the programmable data processing system with a rotate primitive command and multiple data parameters; (b) using the programmable data processing system to perform the steps of; (1) dividing the rectangular bitmap having an odd width W and an odd height H into an upper left quarter A, an upper right quarter B, a lower right quarter C, and a lower left quarter D, the width of A and C being equal to the height of B and D and the height of A and C being equal to the width of B and D; (2) transferring the rotate primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (3) transferring the multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the FIFO memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (4) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-Y,X); (5) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-Y,X) to a pixel in A located at (X,Y); (6) for each pixel in A, using the graphics accelerator chip to perform a logical XOR copy of a pixel in A located at (X,Y) to a pixel in B located at (W-Y,X); (7) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-Y,X) to a pixel in C located at (W-X,H-Y) (8) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in C located at (W-X,H-Y) to a pixel in B located at (W-Y,X); (9) for each pixel in B, using the graphics accelerator chip to perform a logical XOR copy of a pixel in B located at (W-Y,X) to a pixel in C located at (W-X,H-Y); (10) for each pixel in C, using the graphics accelerator chip to perform a logical XOR copy of a pixel in C located at (W-X,H-Y) to a pixel in D located at (H-X,Y); (11) for each pixel in C, using the graphics accelerator chip to perform a logical XOR copy of a pixel in D located at (H-X,Y) to a pixel in C located at (W-X,H-Y); (12) for each pixel in C;
using the graphics accelerator chip to perform a logical XOR copy of a pixel in C located at (W-X,H-Y) to a pixel in D located at (H-X,Y);wherein X varies from 0 to int(W/2) and Y varies from 0 to int(H/2)-1, and wherein the pixels of B are exchanged with the pixels of A, the pixels of C are exchanged with the pixels of B, the pixels of D are exchanged with the pixels of C, the pixels of A are exchanged with the pixels of D in the display memory.
- within a display memory with a graphics accelerator chip using a programmable data processing system having a data input device, a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a FIFO memory and a temporary memory for storing a primitive command, the method comprising the steps of;
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24. A method of drawing a convex polygon with a graphics accelerator chip using a programmable data processing system having a data input device and a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with a vertices list representing the vertices of the polygon; (b) using the programmable data processing system to perform the steps of; (1) searching the vertices list to determine a left top vertex and a right top vertex; (2) setting a current left top vertex equal to the left top vertex and setting a current right top vertex equal to the right top vertex; (3) searching the vertices list to determine a left bottom vertex and a right bottom vertex below the current left top vertex and the current right top vertex; (4) determining a first slope between the current left top vertex and the left bottom vertex, and determining a second slope between the current right top vertex and the right bottom vertex; (5) if the left bottom vertex is at the same height as the right bottom vertex, setting a current bottom height equal to the height of the current left top vertex and the current right top vertex and transferring information defining a first trapezoid bounded by the current left top vertex, the current right top vertex, the current bottom height, the first slope, and second slope from the data processing system to the graphics accelerator chip across the digital data bus, wherein the graphics accelerator chip draws the first trapezoid; (6) if the left bottom vertex is at a greater height than the right bottom vertex, setting the current bottom height equal to the height of the left bottom vertex and transferring information defining a second trapezoid bounded by the current left top vertex, the current right top vertex, the current bottom height, the first slope, and second slope from the data processing system to the graphics accelerator chip across the digital data bus, wherein the graphics accelerator chip draws the second trapezoid; (7) if the right bottom vertex is at a greater height than the left bottom vertex, setting the current bottom height equal to the height of the right bottom vertex and transferring information defining a third trapezoid bounded by the current left top vertex, the current right top vertex, the current bottom height, the first slope, and second slope from the data processing system to the graphics accelerator chip across the digital data bus, wherein the graphics accelerator chip draws the third trapezoid; and (8) if there is a vertex below the current bottom height, setting the height of the current left top vertex and current right top vertex equal to the current bottom height and returning to step (3); wherein the convex polygon is completely drawn by the graphics accelerator chip drawing a combination of the trapezoids.
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25. A method for sending instructions to a graphics accelerator chip using a programmable data processing system having a data input device and a digital data bus capable of transmitting address information and data information, the method comprising the steps of:
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(a) using the data input device to provide the programmable data processing system with input information representing a chip instruction; (b) using the programmable data processing system to perform the steps of; (1) separating the input information into an address portion and a data portion; (2) combining the address portion and the data portion into a single instruction which is formatted to be read by the chip, the single instruction selected from the group consisting of CHIP-- ID, having offset 0x1E00, MODE, having offset 0x1E04, HESYNC/HEBLNK, having offset 0x1E08, HSBLNK/HTOTAL, having offset 0x1E0C, VESYNC/VEBLNK, having offset 0x1E10, VSBLNK/VTOTAL, having offset 0x1E14, VIDCTRL, having offset 0x1E18, VERTICAL-- INTERRUPT, having offset 0x1E1A, DPYBASE, having offset 0x1E1C, FBUFBASE1, having offset 0x1E20, FBUFBASE2, having offset 0x1E24, PZBUFBASE, having offset 0x1E28, ZBUFBASE2, having offset 0x1E2C, MBUFBASE, having offset 0x1E30, DPYPITCH, having offset 0x1E34, MBPITCH, having offset 0x1E36, FBPITCH1/FBPITCH2, having offset 0x1E38, ZBPITCH1/ZBPITCH2, having offset 0x1E3C, PRIMITIVE, having offset 0x1E42, FONT HEIGHT/FONT-- WIDTH, having offset 0x1E44, DRIVER-- SIGNATURE, having offset 0x1E47, LROP, having offset 0x1E48, AROP, having offset 0x1E49, STYLELEN, having offset 0x1E4A, CPATHEIGHT/CPATWIDTH, having offset 0x1E4B, STYLE, having offset 0x1E4C, ZCLIP, having offset 0x1E50, WZOFFSET, having offset 0x1E52, WZOFFSET, having offset 0x1E52, WYOFFSET/WXOFFSET, having offset 0x1E54, WYOFFSET/WXOFFSET, having offset 0x1E54, WYOFFSET/WXOFFSET, having offset 0x1E54, CTOP/CLEFT, having offset 0x1E58, CBOTTOM/CRIGHT, having offset 0x1E5C, Y0/X0, having offset 0x1E60, Y1/X1, having offset 0x1E64, Y2/X2, having offset 0x1E68, Y3/X3, having offset 0x1E6C, FCOLOR, having offset 0x1E70, BCOLOR, having offset 0x1E74, MONOCHROME PATTERN, having offset 0x1E78, FX0, having offset 0x1E80, dFX0, having offset 0x1E84, FX1, having offset 0x1E88, dFX1, having offset 0x1E8C, HZ, having offset 0x1E90, dHZ, having offset 0x1E94, VZ, having offset 0x1E98, dVZ, having offset 0x1E9C, HR, having offset 0x1EA0, dHR, having offset 0x1EA4, VR, having offset 0x1EA8, dVR, having offset 0x1EAC, HG, having offset 0x1EB0, dHG, having offset 0x1EB4, VG, having offset 0x1EB8, dVG, having offset 0x1EBC, HB, having offset 0x1EC0, dHB, having offset 0x1EC4, VB, having offset 0x1EC8, dVB, having offset 0x1ECC, AXIAL-- STEP, having offset 0x1EF0, DIAG STEP, having offset 0x1EF4, INITIAL-- ERR, having offset 0x1EF8, DIR/COUNT, having offset 0x1EFC, FIFO-- WRITE, having offset 0x1F00--1F7F, RESULT-- READ, having offset 0x1F00--1F7F, POWERUP, having offset 0x1F80, MAPO, having offset 0x1F84, MAP1, having offset 0x1F88, FIFO-- PRIMITIVE, having offset 0x1F8E, STATUS, having offset 0x1F90, CONTROL, having offset 0x1F92, INTERRUPT-- STATUS, having offset 0x1F94, and INTERRUPT-- ENABLE, having offset 0x1F96; (3) sending the formatted chip instruction to the graphics accelerator chip using the digital data bus; wherein the graphics accelerator chip receives the formatted chip instruction from the digital data bus and performs the operation designated by the formatted chip instruction.
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26. A method of performing multiple graphics operations with a graphics accelerator chip using a programmable data processing system having a data input device and a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, the graphics accelerator chip having a buffer memory and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) transferring the primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (b) transferring multiple data parameters corresponding to one of the multiple graphics operations from the data processing system to the graphics accelerator chip across the digital data bus into the buffer memory;
(c) using the graphics accelerator chip to perform a graphics operation corresponding to the primitive command stored in the temporary memory and the multiple data parameters stored in the buffer memory; and(d) returning to step (b) if there are ones of the multiple data parameters which have not been transferred from the data processing system to the graphics accelerator chip; wherein the primitive command is transferred from the data processing system to the graphics accelerator chip only once during the performance of the multiple graphics operations.
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27. A method of performing a draw string operation with a graphics accelerator chip which interprets graphics instructions and data received via an external data bus, the graphics accelerator chip being logically coupled to a display memory initialized with a rectangular array of bitmap cells addressable by cell row and cell column, the graphics accelerator chip having a buffer memory for storing multiple data parameters and a temporary memory logically coupled to the external data bus for temporarily storing a draw string graphics command, wherein
the graphics accelerator chip receives a cell column value, a cell row value, and a cell width value from the external data bus into the buffer memory; - and
the graphics accelerator chip transfers pixel signals representative of a portion of a display image from a cell in the display memory corresponding to the cell column value and cell row value stored in buffer memory to a destination location in the display memory, and moves the destination location to a next display location by the value of the cell width value; and the draw string graphics command is transferred to the temporary memory only once during the performance of the draw string operation.
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28. A method of performing a draw string operation with a graphics accelerator chip using a programmable data processing system having a digital data bus capable of transferring information between the data processing system and the graphics accelerator chip, and a display memory initialized with a rectangular array of bitmap cells addressable by cell row and cell column, the graphics accelerator chip having a buffer memory for storing multiple data parameters and a temporary memory for storing a primitive command, the method comprising the steps of:
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(a) transferring a draw string primitive command from the data processing system to the graphics accelerator chip across the digital data bus into the temporary memory; (b) transferring multiple data parameters from the data processing system to the graphics accelerator chip across the digital data bus into the buffer memory, the multiple data parameters including a source point, a destination point, a width value, and a height value; (c) transferring a cell column value, a cell row value, and a cell width value from the data processing system to the graphics accelerator chip across the digital data bus into the buffer memory; (d) using the graphics accelerator chip to transfer pixel signals representative of a portion of a display image from a cell in the display memory corresponding to the cell column value and cell row value stored in buffer memory to a destination location in the display memory, and moving the destination location to a next display location by the value of the cell width value; and (e) returning to step (c) if there are cell column and row values which have not been transferred from the data processing system to the graphics accelerator chip; wherein the draw string primitive command is transferred from the data processing system to the graphics accelerator chip only once during the performance of the draw string operation.
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29. A graphics accelerator chip which interprets graphics instructions and data received via an external data bus, the graphics accelerator chip being logically coupled to a display memory and having a temporary memory logically coupled to the external data bus for temporarily storing a graphics instruction, wherein the graphics accelerator chip:
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performs a logical exclusive-or (XOR) operation on the pixel signal representative of a portion of a display image located at a first location within the display memory to a pixel signal representative of a portion of a display image located at a second location within the display memory; performs a logical XOR operation on the pixel signal representative of a portion of a display image located at the second location within the display memory to the pixel signal representative of a portion of a display image located at the first location within the display memory; and performs a logical XOR operation on the pixel signal representative of a portion of a display image located at the first location within the display memory to the pixel signal representative of a portion of a display image located at the second location within the display memory; wherein the pixel signal representative of a portion of a display image located at the first location within the display memory is exchanged with the pixel signal representative of a portion of a display image located at the second location within the display memory.
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Specification
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Current AssigneeControl Systems Incorporated (Siemens AG)
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Original AssigneeControl Systems Incorporated (Siemens AG)
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InventorsHoug, Todd C., Sluiter, David O., Jackson, Benton H., Becklund, Thomas K., Ukura, John R.
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Primary Examiner(s)Bayerl, Raymond J.
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Assistant Examiner(s)Nguyen, Cao H.
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Application NumberUS08/429,834Time in Patent Office1,111 DaysField of Search395/162, 395/166, 395/163, 395/165, 395/285, 395/126, 395/501, 395/502, 395/516, 395/521, 382/296, 382/297, 345/501, 345/502, 345/516, 345/521, 345/526US Class Current345/503CPC Class CodesG06T 1/20 Processor architectures; Pr...
