Testable chip carrier

• US 5,751,554 A
• Filed: 03/07/1996
• Issued: 05/12/1998
• Est. Priority Date: 01/19/1993
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Williams, Simon Mark, McGeary, Michael Lawrence
• Primary Examiner(s): Ledynh, Bot L.
• Application Number:
  US08/612,206
• Time in Patent Office: 796 Days
• Field of Search: 361/760-764, 361/709, 361/714-715, 361/720-722, 361/772, 361/774, 361/777, 174/52.2, 174/52.3, 174/52.4, 174/250, 174/260-263
• US Class Current: 361/760
• CPC Class Codes: H01L 22/32 Additional lead-in metallisation on a device or substrate, e.g. additional pads or pad portions, lines in the scribe line, sacrificed conductors arrangements for conducting electric current to or from the solid state body in operation H01L23/48
• CPC Class Codes: H01L 2223/54473 for use after dicing
• CPC Class Codes: H01L 2224/05553 being rectangular
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48465 the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
• CPC Class Codes: H01L 2224/48471 the other connecting portion not on the bonding area being a ball bond, i.e. wedge-to-ball, reverse stitch
• CPC Class Codes: H01L 2224/48472 the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
• CPC Class Codes: H01L 2224/4911 the connectors being bonded to at least one common bonding area, e.g. daisy chain
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/10 characterised by the material or arrangement of seals between parts, e.g. between cap and base of the container or between leads and walls of the container
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49838 Geometry or layout
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01006 : Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01014 : Silicon [Si]
• CPC Class Codes: H01L 2924/01027 : Cobalt [Co]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01047 : Silver [Ag]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/10162 : with a square active surface
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/15153 : the die mounting substrate comprising a recess for hosting the device
• CPC Class Codes: H01L 2924/1517 : Multilayer substrate
• CPC Class Codes: H01L 2924/15173 : in a single layer of the multilayer substrate
• CPC Class Codes: H01L 2924/16152 : Cap comprising a cavity for hosting the device, e.g. U-shaped cap
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19107 : off-chip wires
• CPC Class Codes: H01L 2924/3011 : Impedance
• CPC Class Codes: H01L 2924/30111 : matching

Abstract

An integrated circuit handling, packaging and testing apparatus in the form of a testable chip carrier comprising a rigid substrate onto which a chip may be bonded, and which provides a high density interconnect pattern orthogonally aligned to the chip bond pads for wire bonding thereto. The interconnect also provides external bonding points patterned for similar orthogonal alignment to the external device to which the chip is to be connected, and the dimensions of the carrier are substantially smaller than an equivalent standard or custom package type. A hermetic or non-hermetic seal lidding operation may be carried out on the chip and carrier. The carrier also provides a detachable test perimeter allowing full-functional testing and burn-in of the attached wire-bonded chip prior to placement on a printed circuit board or multi-chip module. Signal integrity is improved by the exact alignment of the carrier-to-chip and carrier-to-external device connections, and manufacturing techniques allow for the use of optimum interconnect materials, multi-layer structures and the addition of passive components external to the chip. The carriers may be integrated with heatsinks.

Claims

1. A chip carrier comprising a rigid substrate, at least a first surface thereof being electrically insulating, the planar area of the substrate being divided into three portions:

the first portion adapted for the siting of an integrated circuit chip, the chip having a plurality of bonding pads for electrical connections to the chip;

the second portion bounding said first portion and having a first plurality of conductive traces formed on said first surface thereof;

the third portion bounding said second portion and having a second plurality of conductive traces formed on a first surface thereof, the first conductive traces being electrically connected to corresponding traces of the second plurality of traces in the third portion;

the first conductive traces each terminating, at one end thereof, at inner bonding areas, and fanning out from the inner bonding areas to terminate, at the other end thereof, at outer bonding areas at the outer periphery of the second portion;

characterized by

the inner bonding areas being positioned on the substrate within the first portion or at the inner periphery of the second portion, at positions orthogonally projected outward from each bonding pad of the chip in the plane of the substrate thereby resulting in a substantially identical distance from each bonding pad of a chip sited in said first portion to a corresponding inner bonding area.

2. A chip carrier according to claim 1 wherein the outer bonding areas are positioned on the substrate at positions orthogonally projected inward from a plurality of corresponding connections of an external structure upon which the first and second portions are to be placed for electrical connection to the outer bonding areas resulting in a second substantially identical distance from each outer bonding area to its corresponding connection on the external structure.

3. A chip carrier according to claim 1, wherein each of the second conductive traces terminate, at one end, the electrical connections with the respective first conductive traces, and at the other end terminate at a predetermined contact position, the third portion being detachable from the second portion.

4. A chip carrier according to claim 2 wherein the external structure is a printed circuit board.

5. A chip carrier according to claim 2 wherein the external structure is a multi-chip module.

6. A chip carrier according to claim 3 wherein the third portion has discrete passive components mounted thereon, electrically connected to selected ones of the plurality of second traces.

7. A chip carrier according to claim 6 wherein the third portion has vias cut therethrough from the first surface to a second surface thereof, the second surface being provided with predetermined contact positions for electrical connection to selected ones of the second plurality of traces.

8. A chip carrier according to claim 1 wherein the second portion has discrete passive components mounted thereon, electrically connected to selected ones of the plurality of first traces.

9. A chip carrier according to claim 1 wherein the first portion has discrete passive components mounted thereon, electrically connected to selected ones of the plurality of first traces.

10. A chip carrier according to claim 8 wherein the second portion has vias cut therethrough from the first surface to a second surface thereof, the second surface being used for the mounting of the discrete passive components.

11. A chip carrier according to claim 3 wherein the predetermined contact positions of the second traces emulate pin positions of a standard chip package.

12. A chip carrier according to claim 1 wherein said substrate is constructed from a ceramic material.

13. A chip carrier according to claim 12 wherein said substrate is constructed from one of aluminium nitride, silicon dioxide, beryllium oxide or poly-silicon.

14. A chip carrier according to claim 1 wherein at least a part of the substrate is fabricated with an integral heatsink.

15. A chip carrier according to claim 3 wherein the outer bonding areas are formed as beam lead interconnections, the first plurality of conductive traces extending beyond the outer periphery of the first portion upon detachment of the third portion.

16. A chip carrier according to claim 1 wherein the first portion comprises a recess or void in the substrate into which the chip may be inserted.

17. A chip carrier according to claim 1 wherein the first conductive traces are patterned so as to act as impedance matching connections between the chip and the external structure.

18. A chip carrier according to claim 1 wherein the first conductive traces are patterned with a uniform track spacing and/or pitch.