Automated system and method for identifying critical timing paths in integrated circuit layouts for use with automated circuit layout system

• US 5,751,596 A
• Filed: 07/27/1995
• Issued: 05/12/1998
• Est. Priority Date: 07/27/1995
• Status: Expired due to Fees

• Current Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Ginetti, Arnold, Spyrou, Athanasius W.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): Walker, Tyrone V.
• Application Number:
  US08/495,194
• Time in Patent Office: 1,020 Days
• Field of Search: 395/500, 364/488, 364/489, 364/490, 364/491
• US Class Current: 716/104
• CPC Class Codes: G06F 2119/12 Timing analysis or timing optimisation
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/3312 Timing analysis
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A computer aided design system converts system level timing constraints to the minimum number of path-based timing constraints necessary to represent the same timing constraints as the system level timing constraints. Using a data structure for each node of the circuit, signal arrival times and required arrival times for each node are generated for each high level timing constraint, and the worst slack time is identified for each node. Then, a node with a worst slack time is selected, the constraint associated with that worst slack time is identified, and then a worst case path from a start node of the identified constraint through the selected node to an end node of the identified constraint is determined. The start and required signal arrival times associated with the identified constraint'"'"'s start and end nodes in the determined path are also identified. Then the determined path, and the maximum signal traversal time associated with that path are written to a path-based constraint data structure, and all the nodes in the determined path are marked as having been processed. Additional path-based constraints are generated, each time using an unmarked node having a worst remaining slack time, until all nodes in the circuit netlist having identified slack times have been included in at least one path-based constraint. The set of path-based constraints are used by a circuit layout generator to generate a circuit layout that meets the specified timing constraints.

Claims

1. A method of synthesizing an integrated circuit, the steps of the method comprising:

(A) receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components;

each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;

(B) receiving and storing in a computer memory a plurality of system level timing constraints, said system level timing constraints representing maximum delay times for signals to propagate from input nodes to output nodes of said integrated circuit;

(C) receiving cell delay data representing signal delays associated with said components in said integrated circuit;

(D) for each system timing constraint, storing data for nodes downstream of input nodes associated with said each system timing constraint and for nodes upstream of output nodes associated with said each system timing constraint, said stored data indicative of slack at said nodes with respect to each said system timing constraint;

(E) repeatedly generating successive path-based timing constraints, until all nodes for which slack indicative data has been stored are included in at least one path-based timing constraint, each path-based timing constraint being generated by;

(E1) selecting a node, not included in any previously generated path-based timing constraint, with a worst slack represented in said stored data;

(E2) identifying which system level timing constraint corresponds to a worst slack associated with said selected node; and

(E3) identifying a signal path from a start node associated with said identified system level timing constraint through said selected node to an end node associated with said identified system level timing constraint, determining a path traversal time for said identified signal path-based on said stored data, and outputting said identified signal path and path traversal time as one of said path-based timing constraints; and

(F) passing said netlist and output path-based timing constraints to a silicon compiler and automatically placing/routing a circuit in according with said netlist and path-based timing constraints.

2. A method of synthesizing an integrated circuit, the steps of the method comprising:

(A) receiving and storing in a computer memory a netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components;

each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;

(B) receiving and storing in a computer memory a plurality of system level timing constraints, said system level timing constraints representing maximum delay times for signals to propagate from respective ones of said input nodes to respective ones of said output nodes of said integrated circuit;

(C) receiving cell delay data representing signal delays associated with said components in said integrated circuit;

(D) for each system timing constraint, generating signal arrival time data for nodes downstream of input nodes associated with said each system timing constraint and signal required time data for nodes upstream of output nodes associated with said each system timing constraint, and generating slack data indicative of differences between said generated signal arrival time and signal required time at said nodes with respect to each said system timing constraint;

(E) repeatedly generating successive path-based timing constraints, until all nodes for which slack indicative data has been stored are included in at least one path-based timing constraint, each path-based timing constraint being generated by;

(E1) selecting a node, not included in any previously generated path-based timing constraint;

(E2) identifying which system level timing constraint corresponds to a worst slack associated with said selected node; and

(E3) identifying a signal path from a start node associated with said identified system level timing constraint through said selected node to an end node associated with said identified system level timing constraint, determining a path traversal time for said identified signal path-based on said stored data, and outputting said identified signal path and path traversal time as one of said path-based timing constraints; and

(F) passing said netlist and output path-based timing constraints to a silicon compiler and automatically placing/routing a circuit in according with said netlist and path-based timing constraints.

3. A computer aided circuit design system for synthesizing an integrated circuit, comprising:

(A) a computer memory;

(B) a netlist stored in said computer memory, said netlist denoting a list of components in said integrated circuit and a set of nodes interconnecting said components;

each said component of said integrated circuit having at least one input port and at least one output port, said set of nodes including a set of circuit input nodes and circuit output nodes for said integrated circuit;

(C) a plurality of system level timing constraints stored in said computer memory, said system level timing constraints representing maximum delay times for signals to propagate from respective ones of said input nodes to respective ones of said output nodes of said integrated circuit;

(D) cell delay data stored in said computer memory, said cell delay data representing signal delays associated with said components in said integrated circuit;

(E) a node annotator procedure, executed by said computer system, for processing for each system timing constraint, said node annotator procedure processing said stored netlist and cell delay data to generate signal arrival time data for nodes downstream of input nodes associated with said each system timing constraint and signal required time data for nodes upstream of output nodes associated with said each system timing constraint, and to generate slack data indicative of differences between said generated signal arrival time and signal required time at said nodes with respect to each said system timing constraint;

(F) said node annotator procedure including path-based timing constraint generation instructions for repeatedly generating successive path-based timing constraints, until all nodes for which slack indicative data has been stored are included in at least one path-based timing constraint, said path-based timing constraint generation instructions including instructions for;

(F1) selecting a node, not included in any previously generated path-based timing constraint;

(F2) identifying which system level timing constraint corresponds to a worst slack associated with said selected node; and

(F3) identifying a signal path from a start node associated with said identified system level timing constraint through said selected node to an end node associated with said identified system level timing constraint, determining a path traversal time for said identified signal path-based on said stored data, and outputting said identified signal path and path traversal time as one of said path-based timing constraints; and

(G) a silicon compiler and automatically placing/routing a circuit in according with said netlist and path-based timing constraints.