Memory cell that can store data nonvolatily using a ferroelectric capacitor, and a semiconductor memory device including such a memory cell
First Claim
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1. A memory cell that can store information in a non-volatile manner, comprising:
- a plurality of bit line pairs,a plurality of word lines crossing said bit line pairs,a plurality of bistable memory elements arranged in corresponding crossing of said bit line pairs and said word lines,each of said bistable memory elements includinga first amplifying circuit having an input and an output,and a second amplifying circuit having an output and an input coupled to said input and said output, respectively, of said first amplifying circuit,a node to which a fixed potential is supplied, a first data output node coupled to said output of said first amplifying circuit,a second data output node coupled to said output of said second amplifying circuit,a first ferroelectric capacitor having one end coupled to said second data output node and the other end coupled to said node to which said fixed potential is supplied,a second ferroelectric capacitor having one end coupled to said first data output node and the other end coupled to said node to which said fixed potential is supplied,a first access transistor connected between said first data output node and the first bit line of one of said bit line pairs, anda second access transistor connected between said data output node and the second bit line pairing with said first bit line, andeach of said first and said second access transistors being controlled to be conductive/nonconductive by a potential of corresponding said word line,a plurality of first data output lines, each connected to corresponding said first data output node, anda plurality of second data output lines, each connected to corresponding said second data output node.
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Abstract
In a bistable memory element including a first inverting circuit of an N channel MOSFET and a P channel MOSFET, and a second inverting circuit of an N channel MOSFET and a P channel MOSFET, a memory cell is formed of a first ferroelectric capacitor having one end coupled to the input of the first inverting circuit and the other end coupled to a fixed potential VCP and a second ferroelectric capacitor having one end coupled to the input of the second inverting circuit and the other end coupled to the fixed potential VCP. Since the fixed potential VCP can be varied to an arbitrary value by an external signal, the intensity of the electric field applied to the ferroelectric capacitor can be set to an arbitrary value.
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Citations
12 Claims
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1. A memory cell that can store information in a non-volatile manner, comprising:
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a plurality of bit line pairs, a plurality of word lines crossing said bit line pairs, a plurality of bistable memory elements arranged in corresponding crossing of said bit line pairs and said word lines, each of said bistable memory elements including a first amplifying circuit having an input and an output, and a second amplifying circuit having an output and an input coupled to said input and said output, respectively, of said first amplifying circuit, a node to which a fixed potential is supplied, a first data output node coupled to said output of said first amplifying circuit, a second data output node coupled to said output of said second amplifying circuit, a first ferroelectric capacitor having one end coupled to said second data output node and the other end coupled to said node to which said fixed potential is supplied, a second ferroelectric capacitor having one end coupled to said first data output node and the other end coupled to said node to which said fixed potential is supplied, a first access transistor connected between said first data output node and the first bit line of one of said bit line pairs, and a second access transistor connected between said data output node and the second bit line pairing with said first bit line, and each of said first and said second access transistors being controlled to be conductive/nonconductive by a potential of corresponding said word line, a plurality of first data output lines, each connected to corresponding said first data output node, and a plurality of second data output lines, each connected to corresponding said second data output node.
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2. A memory cell that can store information in a non-volatile manner, comprising:
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a bistable memory element including a first amplifying circuit having an input and an output and a second amplifying circuit having an output and an input coupled to said input and said output, respectively, of said first amplifying circuit, and a ferroelectric capacitor having one end connected between the input of the first amplifying circuit and the output of the second amplifying circuit, and the other end connected between the input of said second amplifying circuit and the output of the first amplifying circuit.
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3. A semiconductor memory device having a redundancy function, comprising:
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a main memory cell array in which a plurality of memory cells are arranged, means responsive to an external input address signal for reading or writing information of one cell in said memory cell array, a spare memory cell array formed of a plurality of memory cells each having a structure identical to that of said memory cell of said main memory cell array, spare cell selecting means for reading/writing information of a corresponding cell in said spare memory cell array when said input address signal corresponds to a defective cell in said main memory cell array, wherein said spare cell selecting means includes spare decoding means for comparing said external input address signal with an address of said defective cell, and selecting said corresponding cell in said spare memory cell array, and defective bit address storing means for storing and outputting said address of said defective cell, wherein said defective bit address storing means includes a plurality of bit line pairs, a plurality of word lines crossing said bit line pairs, a plurality of bistable memory elements arranged in corresponding crossing points of said bit line pairs and said word lines, each of said bistable memory elements including a first amplifying circuit having an input and an output, and a second amplifying circuit having an output and an input coupled to said input and said output, respectively, of said first amplifying circuit, a node to which a fixed potential is supplied, a first data output node coupled to said output of said first amplifying circuit, a second data output node coupled to said output of said second amplifying circuit, a first ferroelectric capacitor having one end coupled to said second data output node and the other end coupled to said node to which said fixed potential is supplied, a second ferroelectric capacitor having one end coupled to said first data output node and the other end coupled to said node to which said fixed potential is supplied, a first access transistor connected between said first data output node and the first bit line of one of said bit line pairs, and a second access transistor connected between said second data output node and the second bit line pairing with said first bit line, and each of said first and second access transistors being controlled to be conductive/nonconductive by a potential of corresponding said word line, said defective bit address storing means further includes, a plurality of first data output lines, each connected between said spare decoding means and said first data output node of corresponding said bistable memory element, and a plurality of second data output lines, each connected between said spare decoding means and said first data output node of corresponding said bistable memory element, and each pair of said first and second data output lines providing corresponding complimentary bit data of said address of said defective cell.
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4. A semiconductor memory device including a redundancy function comprising:
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a main memory cell array in which a plurality of memory cells are arranged, means responsive to an external input address signal for reading or writing information of one cell in said memory cell array, a spare memory cell array formed of a plurality of memory cells each having a structure identical to that of said memory cell of said main memory cell array, spare cell selecting means for reading or writing information of a corresponding cell in said spare memory cell array when said input address signal corresponds to a defective cell in said main memory cell array, wherein said spare cell selecting means includes spare decoding means for comparing said external input address signal with an address of said defective cell, and selecting said corresponding cell in said spare memory cell array, and defective bit address storing means for storing and outputting said address of said defective cell, wherein said defective bit address storing means includes a bistable memory element including a first amplifying circuit having an output and an input, and a second amplifying circuit having an output and an input coupled to said input and output, respectively, of said first amplifying circuit, and a ferroelectric capacitor having one end connected between the input of the first amplifying circuit and the output of the second amplifying circuit, and the other end connected between the input of the second amplifying circuit and the output of the first amplifying circuit.
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5. A semiconductor memory device located in a data transition path between a central processing unit and a main memory unit, said semiconductor memory device having stored data in said main memory unit partially transferred thereto, and to which said central processing unit accesses prior to said main memory unit in a range of said transferred stored data, said semiconductor memory device comprising:
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a memory cell array in which a plurality of memory cells are arranged, wherein each of said plurality of memory cells comprises a bistable memory element including a first amplifying circuit having an input and an output, and a second amplifying circuit having an output and an input coupled to said input and said output, respectively, of said first amplifying circuit, and a ferroelectric capacitor having one end connected between the input of the first amplifying circuit and the output of the second amplifying circuit, and the other end connected between the input of the second amplifying circuit and the output of the first amplifying circuit.
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6. A semiconductor memory device having a redundancy function, comprising:
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a main memory cell array in which a plurality of memory cell are arranged, selecting means responsive to an external input address signal for reading or writing information of one cell in said main memory cell array, means for transmitting a pseudo address signal to said selecting means to write/read information, and carrying out self testing of an acceptable/defective memory cell, a spare memory cell array formed of a plurality of memory cells each having a structure identical to that of said memory cell of said main memory cell array, means for determining correspondence of an address of a defective cell in said main memory cell array with an address in a memory cell to be substituted in said spare memory cell array according to a result of said self testing, spare cell selecting means for reading/writing information of a corresponding cell in said spare memory cell array when said external input address signal corresponds to a defective cell in said main memory cell array, and means for storing correspondence of said address of a defective cell with said address of a memory cell to be substituted in the spare memory cell array, wherein said means for storing correspondence of addresses includes, a plurality of bit line pairs, a plurality of word lines crossing said bit line pairs, a plurality of bistable memory elements arranged in corresponding crossing points of said bit line pairs and said word lines, each of said bistable memory elements including, a first amplifying circuit having an input and an output, and a second amplifying circuit having an output and an input coupled to said input and said output, respectively, of said first amplifying circuit, a node to which a fixed potential is supplied, a first data output node coupled to said output of said first amplifying circuit, a second data output node coupled to said output of said second amplifying circuit, a first ferroelectric capacitor having one end coupled to said second data output node and the other end coupled to said node to which said fixed potential is supplied, a second ferroelectric capacitor having one end coupled to said first data output node and the other end coupled to said node to which said fixed potential is supplied, a first access transistor connected between said first data output node and the first bit line of one of said bit line pairs, and a second access transistor connected between said second data output node and the second bit line pairing with said first bit line, and each of said first and said second access transistors being controlled to be conductive/nonconductive by a potential of corresponding said word line, said means for storing correspondence of address further includes, a plurality of first data output lines, each connected between said spare cell selecting means and said first data output node of corresponding said bistable memory element, and a plurality of second data output lines, each connected between said spare cell selecting means and said first data output node of corresponding said bistable memory element, and each pair of said first and said second data output lines providing corresponding complimentary bit data of said address of said defective cell.
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7. A semiconductor memory device having a redundancy function, comprising:
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a memory cell array in which a plurality of a memory cells are arranged, selecting means responsive to an external input address signal for reading or writing information of one cell in said main memory cell array, means for transmitting a pseudo address signal to said reading/writing means of cell information to read/write information, and carrying out self testing of an acceptable/defective memory cell, a spare memory cell array formed of a plurality of memory cells each having a structure identical to that of said memory cell of said main memory cell array, means for determining correspondence of an address of a defective cell in said main memory cell array with an address in a memory cell to be substituted in said auxiliary memory cell array according to a result of said self testing, spare cell selecting means for reading/writing information of a corresponding cell in said spare memory cell array when said external input address signal corresponds to a defective cell in said main memory cell array, and means for storing correspondence of said address of the defective cell with said address of a memory cell to be substituted in said spare memory cell array, wherein said means for storing correspondence of addresses includes, a bistable memory element including a first amplifying circuit having an input and an output, and a second amplifying circuit having an output and an input coupled to said input and said output, respectively, of said first amplifying circuit, and a ferroelectric capacitor having one end connected between the input of the first amplifying circuit and the output of the second amplifying circuit, and the other end connected between the input of said second amplifying circuit and the output of the first amplifying circuit.
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8. A semiconductor memory device including a plurality of memory cells storing information according to direction of spontaneous polarization of ferroelectrics, wherein each of said plurality of memory cells comprises
a pair of first and second ferroelectric capacitors having each one end connected to a first potential, polarization means for polarizing said first and second ferroelectric capacitors in directions complementary to each other, a first path including serially connected first and second constant current sources, and having a connection node of said first and second constant current sources connected to the other end of said first ferroelectric capacitor, a second path including serially connected third and fourth constant current sources, and having a connection node of said third and fourth constant current sources connected to the other end of said second ferroelectric capacitor, wherein said first and second paths comprise means for maintaining the values of currents flowing through said second and fourth constant current sources in both paths equal, wherein said semiconductor memory device comprises, for at least every one of said memory cell, potential difference detection means for detecting difference between a potential of the connection node of said first and second constant current sources and a potential of the connection node of said third and fourth constant current sources.
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10. A semiconductor memory device including a plurality of memory cells storing information according to direction of spontaneous polarization of ferroelectrics,
wherein each of said plurality of memory cells comprises a ferroelectric capacitor having one end connected to a first potential, polarization means for polarizing said ferroelectric capacitors, a current path including serially connected first and second constant current sources, and having a connection node of said first and second constant current sources connected to the other end of said first ferroelectric capacitor, wherein said semiconductor memory device comprises, for at least every one of said memory cell, potential detection means for detecting a change of a potential level of the connection node of said first and second current sources.
Specification
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Current AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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Original AssigneeMitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
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InventorsOoishi, Tsukasa
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Primary Examiner(s)Dinh, Son T.
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Application NumberUS08/786,378Time in Patent Office480 DaysField of Search365/145, 365/149, 365/200US Class Current365/145CPC Class CodesG11C 11/22 using ferroelectric elementsG11C 14/00 Digital stores characterise...G11C 14/0072 and the nonvolatile element...G11C 29/789 using non-volatile cells or...
