Method of screening hot temperature erase rejects at room temperature
First Claim
1. A method of testing Flash memory devices for erasability at room temperature during wafer sort to screen out those Flash memory devices that would be rejected during elevated temperature testing for erasability during class test thus negating the requirement to test the Flash memory devices for erasability during class test, wherein the Flash memory devices are organized in x number of rows and y number of columns, the method comprising:
- selecting a number of memory cells in a Flash memory device including at least one memory cell from each of the x number of rows and at least one memory cell from the y number of columns;
subjecting the selected number of memory cells to a first sequence of erasure pulses at a first voltage until the selected memory cells are verified erased or until a first maximum number of erasure pulses has been reached;
recording a number of erasure pulses at which the selected memory cells are verified erased if the selected memory cells are verified erased before the first maximum number of erasure pulses has been reached;
subjecting all cells to a margin read to determine if any cell has not been successfully erased;
repairing all cells determined to have not been successfully erased;
subjecting all cells to a second sequence of erasure pulses at a second voltage until all the memory cells are verified erased or until a second maximum number of erasure pulses has been reached;
marking the Flash memory device as passed if all memory cells are verified erased before the second maximum number of erasure pulses has been reached; and
marking the Flash memory device as failed if all memory cells are not verified erased before the second maximum number of erasure pulses has been reached.
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Accused Products
Abstract
In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature erase rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. Selected cells of the memory device are subjected to a first sequence of erasure pulses at a high voltage until the selected cells are verified erased or until a first maximum number of erasure pulses has been reached, recording the number of pulses required to erase the selected cells, reading and repairing any defective memory cells, and subjecting all cells to a second sequence of erasure pulses until all cells are verified erased or until a maximum number of pulses has been reached wherein the second maximum number is a multiple of the recorded number.
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Citations
11 Claims
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1. A method of testing Flash memory devices for erasability at room temperature during wafer sort to screen out those Flash memory devices that would be rejected during elevated temperature testing for erasability during class test thus negating the requirement to test the Flash memory devices for erasability during class test, wherein the Flash memory devices are organized in x number of rows and y number of columns, the method comprising:
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selecting a number of memory cells in a Flash memory device including at least one memory cell from each of the x number of rows and at least one memory cell from the y number of columns; subjecting the selected number of memory cells to a first sequence of erasure pulses at a first voltage until the selected memory cells are verified erased or until a first maximum number of erasure pulses has been reached; recording a number of erasure pulses at which the selected memory cells are verified erased if the selected memory cells are verified erased before the first maximum number of erasure pulses has been reached; subjecting all cells to a margin read to determine if any cell has not been successfully erased; repairing all cells determined to have not been successfully erased; subjecting all cells to a second sequence of erasure pulses at a second voltage until all the memory cells are verified erased or until a second maximum number of erasure pulses has been reached; marking the Flash memory device as passed if all memory cells are verified erased before the second maximum number of erasure pulses has been reached; and marking the Flash memory device as failed if all memory cells are not verified erased before the second maximum number of erasure pulses has been reached. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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Specification