Method of screening hot temperature erase rejects at room temperature

• US 5,751,633 A
• Filed: 05/24/1996
• Issued: 05/12/1998
• Est. Priority Date: 05/24/1996
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Hsia, Edward, Hernandez, Jose H., Suanya, Sayan
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/655,357
• Time in Patent Office: 718 Days
• Field of Search: 365/185.19, 365/185.22, 365/185.29, 365/185.3, 365/185.09
• US Class Current: 365/185.09
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents

Abstract

In a semiconductor manufacturing process for manufacturing memory devices a method of screening hot temperature erase rejects in memory devices during wafer sort at room temperature that would be rejected at class test at high temperature. Selected cells of the memory device are subjected to a first sequence of erasure pulses at a high voltage until the selected cells are verified erased or until a first maximum number of erasure pulses has been reached, recording the number of pulses required to erase the selected cells, reading and repairing any defective memory cells, and subjecting all cells to a second sequence of erasure pulses until all cells are verified erased or until a maximum number of pulses has been reached wherein the second maximum number is a multiple of the recorded number.

Claims

1. A method of testing Flash memory devices for erasability at room temperature during wafer sort to screen out those Flash memory devices that would be rejected during elevated temperature testing for erasability during class test thus negating the requirement to test the Flash memory devices for erasability during class test, wherein the Flash memory devices are organized in x number of rows and y number of columns, the method comprising:

selecting a number of memory cells in a Flash memory device including at least one memory cell from each of the x number of rows and at least one memory cell from the y number of columns;

subjecting the selected number of memory cells to a first sequence of erasure pulses at a first voltage until the selected memory cells are verified erased or until a first maximum number of erasure pulses has been reached;

recording a number of erasure pulses at which the selected memory cells are verified erased if the selected memory cells are verified erased before the first maximum number of erasure pulses has been reached;

subjecting all cells to a margin read to determine if any cell has not been successfully erased;

repairing all cells determined to have not been successfully erased;

subjecting all cells to a second sequence of erasure pulses at a second voltage until all the memory cells are verified erased or until a second maximum number of erasure pulses has been reached;

marking the Flash memory device as passed if all memory cells are verified erased before the second maximum number of erasure pulses has been reached; and

marking the Flash memory device as failed if all memory cells are not verified erased before the second maximum number of erasure pulses has been reached.

2. The method of claim 1, wherein said second maximum number is determined by multiplying said recorded number or said first maximum number by a multiplier.

3. The method of claim 2, wherein said multiplier is in the range of 150 to 300% of said recorded number.

4. The method of claim 3, wherein said first maximum number of pulses is in a range of 400-500.

5. The method of claim 4, further comprising the step of reading each memory cell location and repairing any defective cell detected.

6. The method of claim 5, wherein the first voltage is higher than the second voltage.

7. The method of claim 6, wherein the first voltage is between 12.5 and 13.5 volts.

8. The method of claim 7, wherein the second voltage is between 10.75 and 11.5 volts.

9. The method of claim 1, wherein the step of subjecting all memory cells with a first sequence of erasure pulses at a first voltage until the selected memory cells are verified erased or until a first maximum number of erasure pulses has been reached includes a first short duration dummy read cycle.

10. The method of claim 9, wherein the step of subjecting all memory cells with a second sequence of erasure pulses at a second voltage until all memory cells are verified erased or until a second maximum number of erasure pulses has been reached includes a second short duration dummy read cycle.

11. The method of claim 10, wherein the first and second short duration dummy read cycle have a duration in the range of 100 nanoseconds to 1 microsecond.