Automatic programming algorithm for page mode flash memory with variable programming pulse height and pulse width

• US 5,751,637 A
• Filed: 03/12/1996
• Issued: 05/12/1998
• Est. Priority Date: 06/07/1995
• Status: Expired due to Term

• Current Assignee: Macronix International Co., Ltd.
• Original Assignee: Macronix International Co., Ltd.
• Inventors: Chen, Chia Shing, Hung, Chun-Hsiung, Kamei, Teruhiko, Wan, Ray-Lin
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/605,003
• Time in Patent Office: 791 Days
• Field of Search: 365/45, 365/189.01, 365/189.07, 365/168, 365/185.33
• US Class Current: 365/185.33
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

A method for programming a flash memory array which insures fast programming to substantially all of the cells in the array, without over-programming, based on providing a pattern of program retry pulses which have respective pulse widths and pulse heights which vary according to a pattern. The pattern includes a combination of both increasing pulse widths and increasing pulse heights. The pattern includes a first phase which completes in a specified amount of time including a predetermined number of retries so that substantially all of the cells in the array are programmed within the first phase. A second phase of the patter involves a sequence of higher energy pulses addressed to programming the slowest cells in the array. When used in a page program array, in which individual cells which are programmed fast do not receive subsequent retry pulses, a very fast and reliable programming scheme is achieved.

Claims

1. A method for programming a floating gate memory cell, comprising:

applying a first program pulse to the cell having a first pulse height and a first pulse width selected so that the cell is unlikely to be over-programmed;

determining whether the cell is programmed in response to the first program pulse; and

if not

applying a program retry pulse to the cell;

determining whether the cell is programmed in response to the program retry pulse; and

if not

iteratively applying another program retry pulse to the cell and determining whether the cell is programmed, until the cell is determined to be programmed or a maximum number of retries is made;

wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height, the pattern selected so that the cell is likely to be programmed within a first phase of the pattern including predetermined number of retries less than the maximum number of retries.

2. The method of claim 1, wherein retry pulses in the pattern have respective energies determined by the respective pulse heights and widths, and the respective energies of the pulses successively remain constant or increase during the first phase of the pattern.

3. The method of claim 2, wherein the pulse height during the first phase is constant and greater than the first pulse height, and the pulse width during the first phase successively increases.

4. The method of claim 3, wherein the pulses after the first phase have energies greater than a final pulse of the first phase.

5. The method of claim 1, wherein the floating gate cell has a control gate, a source and a drain, and the first program pulse and program retry pulses are generated by supplying a negative voltage to the control gate and a variable voltage to the drain, such that Fowler-Nordheim tunneling is induced to discharge the floating gate cell.

6. An apparatus for storing data, comprising:

a memory array having a plurality of floating gate cells;

supply circuits, coupled to the memory array, which apply voltages to the plurality of floating gate cells to program the plurality of floating gate cells in the memory cells;

a plurality of bit latches, coupled to bit lines in the memory array, which bit latches provide a buffer for temporary storage of sata values to be programmed at least a portion of a row of floating gate cells in the memory array; and

automatic program circuits, coupled to the memory array, the supply circuits and the plurality of bit latches, which program cells on a selected wordline and on bit lines coupled to a bit latch storing a program value, including circuitry

to apply a first program pulse having a first pulse height and a first pulse width set so that the cells are unlikely to be over-programmed;

to determine whether the cell is programmed in response to the first program pulse; and

if it is, to reset the corresponding bit latch, and if it is not

to apply a program retry pulse to the cell;

to determine whether the cell is programmed in response to the program retry pulse; and

if it is, to reset the corresponding bit latch and if it is not

to interatively apply another program retry pulse to the cell, determine whether the cell is programmed and reset bit latches of programmed cells, until all bit latches in the plurality of bit latches are reset or a maximum number of retries is made;

wherein the cell is programmed and reset bit latches of programmed cells, until all bit latches in the plurality of bit latches are reset or a maximum number of retries is made;

wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height.

7. The apparatus of claim 6, wherein

each row of pluarlity of floating gate cells includes a first page and second page;

and the plurality of bit latches include a page of data to be programmed to the floating gate cells.

8. The apparatus of claim 6, wherein:

the memory array includes at least M word lines and at least N bit lines coupled to the plurality of floating gate cells; and

the plurality of bit latches includes one bit latch for each of the N bit lines;

where N is greater than 32.

9. The apparatus of claim 8, wherein the pattern is selected so that the cells are likely to be programmed within a first phase of the pattern including predetermined number of retries less than the maximum number of retries, and N is greater than 500, and the first phase of the pattern is completed in less than one millisecond.

10. The apparatus of claim 9, wherein N is greater than 1000.

11. The apparatus of claim 6, wherein the pattern is selected so that the cells are likely to be programmed within a first phase of the pattern including predetermined number of retries less than the maximum number of retries, and retry pulses in the pattern have respective energies determined by the respective pulse heights and widths, and the respective energies of the pulses successively remain constant or increase during the first phase of the pattern.

12. The apparatus of claim 11, wherein the pulse height during the first phase is constant and greater than the first pulse height, and the pulse width during the first phase successively increases.

13. The apparatus of claim 11, wherein the pulses after the first phase have energies greater than a final pulse of the first phase.

14. The apparatus of claim 6, wherein the first program pulse and program retry pulses are generated by supplying a negative voltage to the selected wordline and a variable voltage to the bitline, such that Fowler-Nordheim tunneling is induced to discharge the floating gate cell.

15. A method of storing data in a memory array on an integrated circuit having M rows and N columns of floating gate memory cells comprising the steps of:

loading a page buffer on the integrated circuit with a row of input data;

selecting a row of memory cells for programming the input data to the row of memory cells;

applying a first program pulse to cells in the row of memory cells corresponding to input data having a program value in the page buffer;

reading the row of memory cells to verify programming of the input data to the row of memory cells;

resetting the input data in the page buffer of successfully verified memory cells in the row of memory cells; and

if data having a program value remains in the page buffer, then

applying a program retry pulse to the cells in the row of memory cells corresponding to input data having a program value in the page buffer;

reading the row of memory cells to verify programming of the input data to the row of memory cells; and

resetting the input data in the page buffer of successfully verified memory cells in the row of memory cells; and

if data having a program value remains in the page buffer, then

alternatively applying another program retry pulse to the cell and reading and resetting the input data for programmed cells, until the row is determined to be programmed or a maximum number of retries is made;

wherein the program retry pulses have respective pulse widths and pulse heights which vary according to a pattern which includes at least one pulse having pulse width wider than the first pulse width and a pulse height higher than the first pulse height.

16. The method of claim 15, further comprises the step of selecting a subset of the N columns in the row of memory cells for programming the input data.

17. The method of claim 15, wherein the step of programming the row memory cells includes the step of changing charge states stored in the floating gate memory cells when a data program state is stored in the page buffer.

18. The method of claim 15, wherein the pattern is selected so that the cells are likely to be programmed within a first phase of the pattern including predetermined number of retries less than the maximum number of retries, retry pulses in the pattern have respective energies determined by the respective pulse heights and widths, and the respective energies of the pulses successively remain constant or increase during the first phase of the pattern.

19. The method of claim 18, wherein the pulse height during the first phase is constant and greater than the first pulse height, and the pulse width during the first phase successively increases.

20. The method of claim 18, wherein the pulses after the first phase have energies greater than a final pulse of the first phase.

21. The method of claim 15, wherein the floating gate cells have a control gate, a source and a drain, and the first program pulse and program retry pulses are generated by supplying a constant negative voltage to the control gate and a variable voltage to the drain, such that Fowler-Nordheim tunneling is induced to discharge the floating gate cells.

22. The method of claim 15, wherein:

the memory array includes at least M word lines and at least N bit lines coupled to the plurality of floating gate cells; and

the page buffer includes one bit latch for each of the N bit lines;

where N is greater than 32.

23. The method of claim 22, wherein the pattern is selected so that the cells are likely to be programmed within a first phase of the pattern including predetermined number of retries less than the maximum number of retries, and N is greater than 500, and the first phase of the pattern is completed in less than one millisecond.

24. The method of claim 23, wherein N is greater than 1000.