Dynamic memory word line driver
DCFirst Claim
1. A random access memory comprising:
- word lines;
dynamic memory cells, each comprising a charge storage capacitor for storing a Vdd logic level through an access transistor, the access transistors having enable inputs connected to the word lines;
a high voltage supply which supplies a controlled high voltage Vpp greater than Vdd ; and
a word line driver circuit, including a level shifter with latching, which receives word line selection signals at Vdd logic levels to drive and latch first and second word line control signals at Vpp logic levels, each control signal in a respective latch state being pulled down to a low level through an N-channel transistor as the other control signal is latched high through a P-channel pull-up transistor, the control signals being set and reset by pull-down transistors gated only by Vdd level signals, the word line driver circuit applying the controlled high voltage from the high voltage supply to a word line.
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Abstract
A circuit which accurately controls the word line (pass transistor gate) driving voltage to a voltage which is both controlled and is not significantly greater than is needed to drive the word line. The elements of the present invention eliminate the need for a double-boot-strapping circuit, and ensure that no voltages exceed that necessary to fully turn on a memory cell access transistor. Accordingly, voltages in excess of that which would reduce reliability are avoided, and accurate driving voltages are obtained. A DRAM includes word lines, memory cells having enable inputs connected to the word lines, apparatus for receiving word line selecting signals at first logic levels Vss and Vdd, and for providing a select signal at levels Vss and Vdd, a high voltage supply source Vpp which is higher in voltage than Vdd, a circuit for translating the select signals at levels Vss and Vdd to levels Vss and Vpp and for applying it directly to the word lines for application to the enable inputs whereby an above Vdd voltage level on the word line is achieved without the use of double boot-strap circuits.
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Citations
29 Claims
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1. A random access memory comprising:
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word lines; dynamic memory cells, each comprising a charge storage capacitor for storing a Vdd logic level through an access transistor, the access transistors having enable inputs connected to the word lines; a high voltage supply which supplies a controlled high voltage Vpp greater than Vdd ; and a word line driver circuit, including a level shifter with latching, which receives word line selection signals at Vdd logic levels to drive and latch first and second word line control signals at Vpp logic levels, each control signal in a respective latch state being pulled down to a low level through an N-channel transistor as the other control signal is latched high through a P-channel pull-up transistor, the control signals being set and reset by pull-down transistors gated only by Vdd level signals, the word line driver circuit applying the controlled high voltage from the high voltage supply to a word line. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A random access memory comprising:
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word lines; dynamic memory cells, each comprising a charge storage capacitor for storing a Vdd logic level through an access transistor, the access transistors having enable inputs connected to the word lines; a voltage supply which supplies a controlled voltage Vxx having a Vxx voltage difference between logic levels which exceeds a Vdd voltage difference between the Vdd logic levels; and a word line driver circuit, including a level shifter with latching, which receives word line selection signals at Vdd logic levels to drive and latch a control signal at Vxx logic levels, the level shifter comprising a pair of cross-coupled transistors forming a latch driven by a pair of reset transistors complementary to the cross-coupled transistors, the reset transistor being gated only by Vdd level signals, the word line driver circuit applying the control voltage from the voltage supply directly to a selected word line.
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15. A method of selecting a word line in a dynamic random access memory comprising:
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decoding address signals to drive first and second level shifted control signals to logic levels including a voltage level greater than the voltage to be stored in a memory cell and latching the level-shifted control signals, each control signal in a respective latch state being pulled down to a low level through an N-channel transistor as the other control signal is latched high through a P-channel pull-up transistor, the control signal being set and reset by pull-down transistors gated only by Vdd level signals; and from one of the latched, level-shifted control signals applying a controlled high voltage greater than the stored voltage to a selected word line. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27)
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28. A method of selecting a word line in a dynamic random access memory comprising:
decoding address signals to drive level shifted control signals to logic levels having a voltage difference which is greater than the voltage difference between logic levels to be stored in a memory cell and latching the level shifted control signals by latching transistors, the latching transistors being set by reset transistors which are complementary to the latching transistors and gated only by Vdd level signals; and
from the latched, level-shifted control signals, applying a controlled voltage to the selected word line.
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29. A dynamic random access memory (DRAM) comprising:
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bitlines and word lines and memory cells connected to the bitlines and word lines, each memory cell being comprised of an access field effect transistor (FET) having its source-drain circuit connected between a bitline and a high logic level voltage Vdd bit charge storage capacitor, the field effect transistor having a gate connected to a corresponding word line; a high Vpp supply voltage source which is in excess of the high logic level voltage Vdd plus one transistor threshold voltage but less than a transistor damaging voltage; means for receiving only Vdd level logic inputs for selecting the word line and means having an input driven by the selecting means for applying the Vpp supply voltage level directly to the word line through the source-drain circuit of an FET; the means for applying comprising a level shifter connected to said high supply voltage source and comprising a pair of cross-coupled P-channel FET circuits connected between the high Vpp supply voltage source and a pair of control nodes; and level shifter driving means connected between the level shifter and ground and connected to the output of the selecting means, the level shifter driving means comprising a pair of N-channel FET circuits, each having source-drain circuits connected between a corresponding one of said control nodes and ground.
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Specification