On-chip memory redundancy circuitry for programmable non-volatile memories, and methods for programming same

• US 5,751,647 A
• Filed: 02/19/1997
• Issued: 05/12/1998
• Est. Priority Date: 02/13/1995
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: O'Toole, James E.
• Primary Examiner(s): YOO, DO H
• Application Number:
  US08/802,376
• Time in Patent Office: 447 Days
• Field of Search: 365/200, 365/233.5, 365/201, 365/236, 365/230.08, 365/189.05, 365/185.09
• US Class Current: 365/200
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 29/44 Indication or identification of errors, e.g. for repair
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/765 in solid state disks
• CPC Class Codes: G11C 29/82 for EEPROMs

Abstract

A programmable non-volatile memory device includes a memory array of addressable memory cells and multiple redundant memory cells for replacing defective memory cells in the memory array. To program the memory device, data is written to one or more of the addressable memory cells in the memory array. In the event that the data is not validly written into the address memory cells, repeated attempts are made to program the same memory cells. The memory device includes a counter for counting the number of times the same memory cells are accessed for programming purposes. When a predetermined number of such programming cycles is achieved, the address memory cells are determined to be defective. A redundancy address matching circuit is enabled at this point to replace the defective memory cells with redundant memory cells that can be validly programmed. The memory device subsequently routes the data to the redundant memory cells instead of the defective memory cells. A system including a programming machine and the programmable non-volatile memory device, and methods for programming such memory devices, are also disclosed.

Claims

1. A programmable non-volatile memory device comprising:

a memory array of memory cells;

a controller programming one of the memory cells with data, the controller repeatedly attempting to program the one memory cell in the event that the data is not validly written into the one memory cell;

a redundant memory cell;

a counter counting the number of attempts the controller makes to program the one memory cell;

means for generating a redundancy enable signal when the number of attempts counted by the counter reaches a predetermined value; and

means for replacing the one memory cell with the redundant memory cell in response to the redundancy enable signal.

2. A programmable non-volatile memory device in accordance with claim 1 and further comprising an address buffer coupled to the memory array and holding an address to select at least one of the memory cells of the array, and wherein the replacing means comprises a redundancy address matching circuit coupled to the counter and the address buffer and managing substitution of the replaced memory cell with the redundant memory cell.

21. A method according to claim 1 and further comprising:

supplying a new address of a byte of memory cells within the memory array to the address input;

and using the new address to;

initiate a programming cycle within the memory device in response to the program attempt by accessing the byte of memory cells using the new address at the address input and writing the data from the data input into the byte of memory cells at the new address;

monitor the memory device to determine whether the data was validly written into the byte of memory cells at the new address;

in the event the data is not validly written into the byte of memory cells at the new address, continue to attempt to program the memory device using the same supplied new address and the data for a predetermined number of programming attempts in an effort to validly program the memory device, each programming attempt causing initiation of a programming cycle within the memory device;

count the number of programming cycles made within the memory device;

replace the byte of memory cells at the new address with the byte of redundant memory cells when the number of programming cycles reaches a predetermined number indicating that the byte of memory cells at the new address is defective; and

correlate within the memory device an address of the byte of redundant memory cells with the new address of the byte of defective memory cells at the address input.

3. A programmable non-volatile memory device comprising:

a memory array of memory cells;

a controller programming one of the memory cells with data, the controller repeatedly attempting to program the one memory cell in the event that the data is not validly written into the one memory cell;

a redundant memory cell;

a counter counting the number of attempts the controller makes to program the one memory cell;

circuitry generating a redundancy enable signal when the number of attempts counted by the counter reaches a predetermined value; and

circuitry replacing the one memory cell with the redundant memory cell in response to the redundancy enable signal.

4. A programmable non-volatile memory device in accordance with claim 3 and further comprising an address buffer coupled to the memory array and holding an address to select at least one of the memory cells of the array, and wherein the replacing circuitry comprises a redundancy address matching circuit coupled to the counter and the address buffer and managing substitution of the replaced memory cell with the redundant memory cell.

5. An integrated circuit comprising:

a programmable non-volatile integrated circuit memory device having a memory array of addressable memory cells, having multiple redundant memory cells which can be selected to replace defective memory cells in the memory array, and having an address buffer coupled to the memory array, the address buffer holding an address to select a memory cell in the memory array;

a programming device programming the non-volatile memory device such that, in the event that one of the memory cells addressed by the address buffer is not validly programmed, the programming device continues to program that memory cell for a predetermined number of programming attempts in an effort to validly program that memory cell;

a counter for counting a number of internal programming cycles that the programming device initiates to the same address, the counter outputting a redundancy enable signal when the number of internal programming cycles reaches a predetermined number, the predetermined number of internal programming cycles being less than or equal to the predetermined number of programming attempts; and

a redundancy address matching circuit operatively coupled to the counter and the address buffer for managing the replacement of the defective memory cells in the memory array with the redundant memory cells by directing data to the redundant memory cells instead of to the defective memory cells.

6. An integrated circuit in accordance with claim 5 wherein the predetermined number of internal programming cycles is less than the predetermined number of programming attempts.

7. An integrated circuit in accordance with claim 5 wherein the predetermined number of internal programming cycles is five or less and the predetermined number of programming attempts is twenty-five or less.

8. An integrated circuit in accordance with claim 5 wherein the redundancy address matching circuit resets the counter upon assigning one of the redundant memory cells for a memory cell for which the redundancy enable signal was generated.

9. An integrated circuit comprising:

a programmable non-volatile memory device having a memory array of addressable memory cells and multiple redundant memory cells;

a programming device for programming the programmable non-volatile memory device and for subsequently monitoring the memory device to determine whether the memory device has been validly programmed;

the programming device programming individual memory cells in the memory device such that in the event that the memory cells are not validly programmed, the programming device continues to attempt to program the same memory cells for a predetermined, non-variable number of programming attempts in an effort to validly program the memory cells;

the programmable non-volatile memory device further comprising;

an address buffer coupled to the memory array to hold a selected address to one or more memory cells in the memory array;

a data buffer coupled to the memory array to hold data to be input into the memory cells at the selected address;

a controller configured to initiate an internal programming cycle to program the memory array in response to the programming attempts made by the programming device, the internal programming cycle including accessing the memory array at the selected address held in the address buffer and writing the data held in the data buffer into the memory cells at the selected address, the controller, in the event that the data is not validly written into the addressed memory cells, repeatedly initiating the programming cycle for the same addressed memory cells in response to the continued programming attempts made by the programming device;

a counter configured to count a number of internal programming cycles that the controller initiates to the same address, the counter outputting a redundancy enable signal when the number of programming cycles reaches a non-variable predetermined number indicating that the addressed memory cells are defective, the predetermined number of internal programming cycles being less than or equal to the predetermined number of programming attempts; and

a redundancy address matching circuit operatively coupled to the counter and the address buffer for managing the replacement of the defective memory cells in the memory array with the redundant memory cells, the redundancy address matching circuit assigning the redundant memory cells for the defective memory cells upon receipt of the redundancy enable signal from the counter, the redundancy address matching circuit storing the addresses of the defective memory cells and comparing subsequent addresses held in the address buffer with the stored addresses and substituting the redundant memory cells when a match occurs, whereby the memory device subsequently routes the data to the redundant memory cells instead of to the defective memory cells.

10. An integrated circuit in accordance with claim 9 wherein the predetermined number of internal programming cycles is less than the predetermined number of programming attempts.

11. An integrated circuit in accordance with claim 9 wherein the predetermined number of internal programming cycles is less than six, and the predetermined number of programming attempts is less than twenty-six.

12. An integrated circuit in accordance with claim 9 wherein the redundancy address matching circuit resets the counter upon replacing the redundant memory cells for the defective memory cells.

13. A system comprising:

a programmable non-volatile memory device having a memory array of addressable memory cells for storing electronic data and multiple redundant memory cells for replacing defective memory cells in the memory array; and

a programming device for programming the programmable non-volatile memory device and for subsequently monitoring the memory device to determine whether the memory device has been validly programmed, the programming device operating according to an algorithm for programming individual memory cells in the memory device where in the event that the memory cells are not validly programmed, the programming device continues to program the same memory cells for a predetermined number of programming attempts in an effort to validly program the memory cells;

the programmable non-volatile memory device further comprising;

an address buffer coupled to the memory array for holding a selected address to one or more memory cells in the memory array;

a data buffer coupled to the memory array for holding data to be input into the memory cells at the selected address;

a controller for initiating an internal programming cycle to program the memory array in response to the programming attempts made by the programming device, the internal programming cycle including accessing the memory array at the selected address held in the address buffer and writing the data held in the data buffer into the memory cells at the selected address;

the controller, in the event that the data is not validly written into the addressed memory cells, repeatedly initiating the programming cycle for the same addressed memory cells in response to the continued programming attempts made by the programming device;

a counter for counting a number of internal programming cycles that the controller initiates to the same address, the counter outputting a redundancy enable signal when the number of programming cycles reaches a predetermined number indicating that the addressed memory cells are defective, the predetermined number of internal programming cycles being less than or equal to the predetermined number of programming attempts;

a redundancy address matching circuit operatively coupled to the counter and the address buffer for managing the replacement of the defective memory cells in the memory array with the redundant memory cells, the redundancy address matching circuit assigning the redundant memory cells for the defective memory cells in response to receipt of the redundancy enable signal from the counter wherein the redundancy address matching circuit stores the addresses of the defective memory cells and compares subsequent addresses held in the address buffer with the stored addresses and substitutes the redundant memory cells when a match occurs; and

the memory device subsequently routing the data to the redundant memory cells instead of to the defective memory cells.

14. A method for programming a non-volatile memory device comprising:

providing a memory array of addressable memory cells;

providing a redundant memory cell for replacing a defective memory cell in the memory array;

addressing a memory cell within the memory array according to a selected address;

writing data to the addressed memory cell;

detecting whether the data is validly written into the addressed memory cell;

in the event that the data is not validly written into the addressed memory cell, re-writing the data to the same addressed memory cell in an attempt to validly write the data into the same addressed memory cell within the memory array;

counting a number of attempts to write the data to the same addressed memory cell; and

replacing the addressed memory cell with the redundant memory cell when the number of attempts reaches a fixed number.

15. A method according to claim 14 and further comprising storing the selected address of the addressed memory cell that is replaced by the redundant memory cell.

16. A method according to claim 14 and further comprising:

storing the selected address of the addressed memory cell that is replaced by the redundant memory cell;

comparing a subsequent address with the stored address; and

substituting the redundant memory cell when a match occurs so that the data will be routed to the redundant memory cell rather than to the defective memory cell.

17. A method for programming a non-volatile integrated circuit memory device comprising:

providing the non-volatile integrated circuit memory device having a memory array of addressable memory cells for storing electronic data, a byte of redundant memory cells for replacing a byte of defective memory cells in the memory array, a data input, and an address input;

supplying an address of a byte of memory cells within the memory array to the address input;

supplying data to the data input;

commencing an attempt to program the memory device using the supplied data and address;

initiating a programming cycle within the memory device in response to the program attempt by accessing the byte of memory cells using the address at the address input and writing the data from the data input into the byte of memory cells at the address;

monitoring the memory device to determine whether the data was validly written into the byte of memory cells;

in the event the data is not validly written into the byte of memory cells, continuing to attempt to program the memory device using the same supplied address and data for a predetermined number of programming attempts in an effort to validly program the memory device, each programming attempt causing initiation of a programming cycle within the memory device;

counting the number of programming cycles made within the memory device;

replacing the addressed byte of memory cells with the byte of redundant memory cells when the number of programming cycles reaches a predetermined number indicating that the addressed byte of memory cells is defective;

correlating within the memory device an address of the byte of redundant memory cells with the address of the byte of defective memory cells at the address input; and

after said replacing and correlating, initiating a programming cycle within the memory device in response to a subsequent program attempt by writing the data from the data input into the byte of redundant memory cells correlated to the address of the byte of defective memory cells at the address input.

18. A method according to claim 17 wherein the replacing occurs when the number of programming cycles reaches a number less than the predetermined number of programming attempts.

19. A method according to claim 17 wherein the replacing occurs when the predetermined number of programming cycles is being five or less and the predetermined number of programming attempts is twenty-five or less.

20. A method according to claim 17 wherein the correlating comprises storing the address of the defective byte of memory cells within the memory device.