Digital information processing device

• US 5,751,711 A
• Filed: 03/26/1996
• Issued: 05/12/1998
• Est. Priority Date: 03/27/1995
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Sakaue, Kenji
• Primary Examiner(s): Kizou, Hassan
• Assistant Examiner(s): BNIMOUSSA, ABDELHAMID
• Application Number:
  US08/621,579
• Time in Patent Office: 777 Days
• Field of Search: 370/362, 370/364, 370/423, 370/431, 370/442, 370/445, 370/498, 395/287, 395/280, 395/306
• US Class Current: 370/431
• CPC Class Codes: H04L 12/5601 Transfer mode dependent, e.g. ATM
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5672 Multiplexing, e.g. coding, scrambling
• CPC Class Codes: H04L 2012/5681 Buffer or queue management
• CPC Class Codes: H04L 49/106 using space switching, e.g. crossbar or matrix
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

In an ATM cell processing device having a data transfer LSI capable of transferring ATM cells, and receiver LSIs capable of receiving the ATM cells having a same content, each data receiver LSI has a data input buffer, a data output buffer connected to the output side of the data input buffer and the input side of the data input buffer is connected to the output side of the data output buffer in the preceding data receiver LSI, and the output side of the data output buffer is connected to the input side of the data input buffer in the following data receiver LSI to form a data transfer path having a cascade connection so that the data of a same content transferred from the data transfer LSI is received in each of the data receiver LSIs in order.

Claims

1. A digital information processing device, comprising:

a data transfer Large Scale Integration (LSI) capable of transferring data; and

a plurality of data receiver LSIs connected in a cascade connection to each other and capable of receiving said data having a same content transferred from said data transfer LSI, each of said plurality of data receiver LSIs comprising;

a data input buffer for receiving said data; and

a data output buffer connected to an output side of said data input buffer,

wherein an output side of said data output buffer in one of said plurality of data receiver LSIs is connected to an input side of said data input buffer in another one of said plurality data receiver LSIs in a following stage in order to form a data transfer path having a cascade connection, and

wherein said data transfer LSI transfers said data to said data input buffer in said data receiver LSI in a first stage in said plurality of data receiver LSIs, each of said plurality of data receiver LSIs further comprising a changeable delay means incorporated between said data input buffer and said data output buffer in each data receiver LSI through which said data is delayed by a time corresponding to its own stage number counted from said data transfer LSI in said data transfer path having said cascade connection, and thereby each of said plurality of receiver LSIs stores said data transferred from said data transfer LSI by delaying a storing operation by the corresponding delay time.

2. A digital information processing device as claimed in claim 1, wherein each of said plurality of data receiver LSIs further comprises detection means for checking whether or not said data transferred from said data transfer LSI is transferred to its own, after a checking operation by said detection means in each data receiver LSI, said data receiver LSI stores therein said data only when said data is transferred to its own from said data transfer LSI.

3. A digital information processing device as claimed in claim 2, wherein said data transfer LSI is capable of transferring packet data based on an ATM cell format as said data to be transferred, and each of said plurality of data receiver LSIs is capable of receiving and processing said packet data.

4. A digital information processing device as claimed in claim 1, wherein said changeable delay circuit comprises a flip-flop circuit, said data transfer path is made up of said plurality of data receiver LSIs connected in the cascade connection, and said flip-flop circuit forming said changeable delay means is incorporated between said data input buffer and said data output buffer.

5. A digital information processing device as claimed in claim 4, wherein said data transfer LSI is capable of transferring packet data based on an ATM cell format as said data to be transferred, and each of said plurality of data receiver LSIs is capable of receiving and processing said packet data.

6. A digital information processing device as claimed in claim 1, wherein said data transfer LSI is capable of transferring packet data based on an ATM cell format as said data to be transferred, and each of said plurality of data receiver LSIs is capable of receiving and processing said packet data.

7. A digital information processing device, comprising:

a data transfer Large Scale Integration (LSI) capable of transferring data; and

a plurality of data receiver LSIs connected in a cascade connection to each other and capable of receiving said data having a same content transferred from said data transfer LSI, each of said plurality of data receiver LSIs comprising;

a data input buffer for receiving said data; and

a data output buffer connected to an output side of said data input buffer,

wherein an output side of said data output buffer in one of said plurality of data receiver LSIs is connected to an input side of said data input buffer in another one of said plurality data receiver LSIs in a following stage in order to form a data transfer path having a cascade connection, and

wherein in said data transfer path having said cascade connection, said data transfer LSI transfers said data to said data receiver LSI in a first stage in said plurality of data receiver LSIs, and said data receiver LSI in the first stage receives only said data having the same content and stores said data into said data input buffer in said data receiver LSI in the preceding stage.

8. A digital information processing device as claimed in claim 7, wherein said data transfer LSI is capable of transferring packet data based on an ATM cell format as said data to be transferred, and each of said plurality of data receiver LSIs is capable of receiving and processing said packet data.

9. A digital information processing device as claimed in claim 7, wherein said data transfer LSI further comprising a bit clock buffer for transferring a bit clock and each of said plurality of data receiver LSIs comprising a bit clock buffer for receiving said bit clock transferred from said data transfer LSI through said data receiver LSIs in preceding stages, and said data transfer LSI and said plurality of data receiver LSIs operate synchronously to each other.

10. A digital information processing device as claimed in claim 7, wherein said data transfer LSI further comprising a system clock buffer for receiving a system clock and each of said plurality of data receiver LSIs comprising a system clock buffer for receiving said system clock, and said data transfer LSI and said plurality of data receiver LSIs operate in synchronism with said system clock to each other.

11. A digital information processing device, comprising:

a data transfer Large Scale Integration (LSI) capable of transferring data; and

a plurality of data receiver LSIs connected in a cascade connection to each other and capable of receiving said data having a same content transferred from said data transfer LSI, each of said plurality of data receiver LSIs comprising;

a data input buffer for receiving said data; and

a data output buffer connected to an output side of said data input buffer,

wherein an output side of said data output buffer in one of said plurality of data receiver LSIs is connected to an input side of said data input buffer in another one of said plurality data receiver LSIs in a following stage in order to form a data transfer path having a cascade connection, and

wherein said data transfer LSI transfers data, including an identifier or identifiers designating at least one of said data receiver LSIs of said plurality of data receiver LSIs to said data input buffer in said data receiver LSI in a first stage in said data transfer path having said cascade connection, and each of said plurality of data receiver LSIs further comprises detection means for checking whether or not said data has been transferred from said data transfer LSI, after a checking operation in each data receiver LSI, said data receiver LSI receives and stores said data therein only when said data has been transferred from said data transfer LSI.

12. A digital information processing device as claimed in claim 11, wherein said data transfer LSI is capable of transferring packet data based on an ATM cell format as said data to be transferred, and each of said plurality of data receiver LSIs is capable of receiving and processing said packet data.

13. A digital information processing device, comprising:

a data transfer Large Scale Integration (LSI) capable of transferring data; and

a plurality of data receiver LSIs connected in a cascade connection to each other and capable of receiving said data having a same content transferred from said data transfer LSI, each of said plurality of data receiver LSIs comprising;

a data input buffer for receiving said data; and

a data output buffer connected to an output side of said data input buffer,

wherein an output side of said data output buffer in one of said plurality of data receiver LSIs is connected to an input side of said data input buffer in another one of said plurality data receiver LSIs in a following stage in order to form a data transfer path having a cascade connection, and

wherein said data transfer LSI is capable of transferring packet data based on an ATM cell format as said data to be transferred, and each of said plurality of data receiver LSIs is capable of receiving and processing said packet data.

14. An ATM cell processing device, comprising:

a first Large Scale Integration (LSI) for transferring data in the form of cells;

a second LSI for receiving data transferred from said first LSI and comprising second buffer means and a second cell input circuit; and

a third LSI for receiving data transferred from said first LSI through said second LSI and comprising third buffer means connected to said second buffer means in a cascade connection and a third cell input circuit,

wherein said second LSI receives all the data transferred from said first LSI by said second buffer means and stores said data in said second cell input circuit,

wherein said third LSI receives all the data transferred from said first LSI through said second buffer means and said third buffer means and stores said data in said third cell input circuit.