Integrated circuit design for a personal use wireless communication system utilizing reflection

• US 5,751,820 A
• Filed: 04/02/1997
• Issued: 05/12/1998
• Est. Priority Date: 04/02/1997
• Status: Expired due to Term

• Current Assignee: James Anderson
• Original Assignee: ReSound Corp. (GN Store Nord A/S)
• Inventors: Taenzer, Jon C.
• Primary Examiner(s): LE, HUYEN D
• Application Number:
  US08/832,573
• Time in Patent Office: 405 Days
• Field of Search: 381/68, 381/68.2, 381/68.4, 381/23.1, 381/68.6, 381/68.7, 455/66, 455/100, 455/575, 455/90
• US Class Current: 381/312
• CPC Class Codes: H04R 25/558 Remote control, e.g. of amplification, frequency

Abstract

An integrated circuit chip set design for a wireless hearing aid communication system including a battery operated transceiver unit worn in the vicinity of the ear of the user and a compact battery operated transmitter/receiver unit worn by or in close range of the user. The basis of the integrated circuit chip set design is to optimize circuit size, speed, power, and manufacturability for a personal use wireless audio communication system using the reflective transmission technology. Power and speed consideration of the circuits are designed to accommodate wireless audio RF reflective transmissions for a close range to the user. The transceiver and the receiver of the system are designed to switch between certain transmission states in order to facilitate rapid switching between a first mode in which the transmitter is transmitting to the receiver and a second mode in which the transceiver is transmitting to the receiver. The circuits are also integrated using a GaAs process and are operated in the multi-GHz range so that the circuits dissipate relatively low power.

Claims

1. An integrated circuit chip set for a personal two-way wireless communication system including a transmitter, a receiver, and a transceiver, said communication system having a first non-reflective mode of operation wherein said transmitter transmits a modulated uplink signal representing a first set of digitized signals to said transceiver and having a second reflective mode of operation wherein said transceiver transmits a modulated downlink signal representing a second set of digitized signals to said receiver, said chip set comprising:

at least two integrated circuit chips including;

a transmitter integrated circuit portion for transmitting said modulated uplink signal to said transceiver during said first mode and for transmitting an unmodulated signal to said transceiver during said second mode;

a receiver integrated circuit portion having a receiver non-receive state and a receiver receive state in which said receiver is receiving said modulated downlink signal from said transceiver, wherein said receiver circuit portion switches from said non-receive state to said receive state in a first minimum time interval;

a transceiver integrated circuit portion for, in a transceiver receive state, receiving said uplink signal from said transmitter and in a transceiver transmit state for receiving and simultaneously modulating said unmodulated signal so as to generate and transmit said modulated downlink signal to said receiver, wherein said transceiver circuit portion switches from said transceiver transmit state to said transceiver receive state in a second minimum time interval and switches from said transceiver receive state to said transceiver transmit state in a third minimum time interval;

wherein said first, second, and third minimum time intervals have a duration such that said system operates essentially as a full duplex system as perceived by a system user.

2. The chip set as described in claim 1 wherein one of said first set of digital signals and said second set of digital signals are audio digital signals and the other of said first set of digital signals and said second set of digital signals are digital data signals.

3. The chip set as described in claim 1 wherein said first set of digital signals and said second set of digital signals are audio digital signals.

4. The chip set as described in claim 1 wherein said first, second, and third time intervals are in the range of 5 to 10 micro seconds.

5. The chip set as described in claim 1 wherein said chip set is operated at a power such that said system transmissions are within close range of said system user.

6. The chip set as described in claim 5 wherein said transmissions are performed less than 50 feet.

7. The chip set as described in claim 5 wherein said transmissions are performed between 1 to 5 feet.

8. The chip set as described in claim 1 wherein said transceiver circuit portion has a corresponding power supply in the range of 3.0 volts with a typical current usage in the range of 100 mA to 150 mA.

9. The chip set as described in claim 1 wherein said transmitter and receiver integrated circuit portions have a high power dissipation mode and a low power dissipation mode wherein portions of each of said transmitter and receiver circuit portions are essentially disabled or partially shut-down when in said low power dissipation mode.

10. The chip set as described in claim 9 wherein said transceiver integrated circuit portion is in a ready state at all times.

11. The chip set as described in claim 9 wherein said transceiver integrated circuit portion has a high power dissipation mode and a low power dissipation mode wherein portions of said transceiver integrated circuit portion are disabled or partially shut-down when said transceiver integrated circuit portion is in said low power dissipation mode.

12. The chip set as described in claim 1 wherein said transmitter circuit portion includes an amplifier stage and wherein in said first mode said amplifier state has a first gain having an associated magnitude and amplifies said modulated uplink signal and in said second mode said amplifier stage has a second gain having an associated magnitude and amplifies said unmodulated signal wherein said second gain magnitude is greater than said first gain magnitude.

13. The chip set as described in claim 1 wherein said transmitter circuit portion and said receiver circuit portion are integrated onto a single one of said at least two chips.

14. The chip set as described in claim 1 wherein said transmitter circuit portion and said receiver circuit portion are integrated onto separate ones of said at least two chips.

15. The chip set as described in claim 1 wherein said transmitter circuit portion is divided onto more than one chip of said at least two chips.