Microprocessor integrated circuit working in internal ROM and external RAM mode

• US 5,751,940 A
• Filed: 01/03/1991
• Issued: 05/12/1998
• Est. Priority Date: 01/09/1990
• Status: Expired due to Term

• Current Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Original Assignee: SGS-Thomson Microelectronics (STMicroelectronics NV)
• Inventors: Nicolai, Jean
• Primary Examiner(s): Treat, William M.
• Application Number:
  US07/638,173
• Time in Patent Office: 2,686 Days
• Field of Search: 395/800, 395/500, 395/183.03, 371/325, 371/16.1, 371/16.2, 371/21.1, 371/22.1, 365/201
• US Class Current: 714/27
• CPC Class Codes: G06F 11/2236 to test CPU or processors
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers

Abstract

Integrated circuits can have both a microprocessor and an internal read-only memory of programs on one and the same chip. To facilitate the perfecting and finalizing of the programs of the read-only memory without undertaking the manufacture, for the perfecting and finalizing operation, of a special version of the circuit that is far too different from the definitive version, an external memory is used for the perfecting and finalizing operation. A contact pad of the chip is used for the transmission, in series mode, of a program coming from an external memory. A mode selection pad makes it possible to define whether the microprocessor must work in internal ROM mode (the normal mode) or in external ROM mode (the mode for the perfecting and finalizing operation). The circuit elements added to enable this dual operation take up little space, so that the definitive version of a circuit can be identical to the provisional perfecting and finalizing version, except that the definitive version contains a definitive program in the read-only memory. The content of the read-only memory can be defined by a single mask and, consequently, only a single different mask will have to be made for the definitive version.

Claims

1. An integrated circuit component comprising an integrated circuit chip encapsulated in a package having external pins, said integrated circuit comprising

a microprocessor,

a program read-only memory to contain a program to be carried out by the microprocessor and

pads, capable of being connected to said external pins of said package, including

at least one serial transmission contact pad, connected to said microprocessor for the serial transmission of addresses and data to and from said microprocessor, and

at least one mode selection contact pad for selecting the mode of operation of the microprocessor,

said integrated circuit further comprising a mode selection circuit to select between first and second possible modes of operation of said microprocessor as a function of a signal present at said mode selection contact pad,

said first mode of operation being the execution of a program which is serially interfaced to said microprocessor through said serial transmission pad,

said second mode of operation being the execution of a program contained in said program read-only memory;

and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to an external pin of the packages;

whereby said first mode of operation is inoperative in said package.

2. An integrated circuit chip in accordance with claim 1 wherein said mode selection contact pad is connected through a resistive circuit element to a voltage supply terminal of said integrated circuit.

3. An integrated circuit chip in accordance with claim 1 wherein said mode selection contact pad is connected through a transistor to a voltage supply terminal of said integrated circuit.

4. An integrated circuit chip in accordance with claim 1 wherein said mode selection circuit comprises a multiplexer controlled by the signal at said mode selection contact pad to select one of said two possible modes of operation of the microprocessor.

5. An integrated circuit chip in accordance with claim 1 further comprising a parallel/series converter and a series/parallel converter connected between said microprocessor and said transmission contact pad.

6. An integrated circuit chip in accordance with claim 1 further comprising a synchronizing contact pad to transmit a synchronizing signal defining the nature of the signals at said transmission contact pad so as to distinguish between addresses and data.

7. An integrated circuit chip in accordance with claim 1 wherein said mode selection circuit comprises a multiplexer controlled by the signal at said mode selection contact pad to select one of said two possible modes of operation of the microprocessor, and wherein said mode selection contact pad is connected through a transistor to a voltage supply terminal of said integrated circuit.

8. An integrated circuit chip in accordance with claim 1 wherein said mode selection circuit comprises a multiplexer controlled by the signal at said mode selection contact pad to select one of said two possible modes of operation of the microprocessor, and wherein said integrated circuit further comprises a parallel/series converter and a series/parallel converter connected between said microprocessor and said transmission contact pad.

9. An integrated circuit chip in accordance with claim 1 wherein said mode selection circuit comprises a multiplexer controlled by the signal at said mode selection contact pad to select one of said two possible modes of operation of the microprocessor, and wherein said chip further comprises a synchronizing contact pad to transmit a synchronizing signal defining the nature of the signals at said transmission contact pad so as to distinguish between addresses and data.

10. An integrated circuit chip in accordance with claim 9 further comprising a parallel/series converter and a series/parallel converter connected between said microprocessor and said transmission contact pad.

11. An integrated circuit chip in accordance with claim 10 wherein said mode selection contact pad is connected through a resistive circuit element to a voltage supply terminal of said integrated circuit.

12. An integrated circuit chip in accordance with claim 10 wherein said mode selection contact pad is connected through a transistor to a voltage supply terminal of said integrated circuit.

13. An integrated circuit package having encapsulated therein a chip in accordance with claim 1, said package having external pins for connections to said integrated circuit on said chip, and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to an external pin of the package.

14. An integrated circuit package having encapsulated therein a chip therein a chip in accordance with claim 4, said package having external pins for connections to said integrated circuit on said chip, and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to an external pin of the package.

15. An integrated circuit package having encapsulated therein a chip in accordance with claim 5, said package having external pins for connections to said integrated circuit on said chip, and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to an external pin of the package.

16. An integrated circuit package having encapsulated therein a chip in accordance with claim 6, said package having external pins for connections to said integrated circuit on said chip, and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to an external pin of the package.

17. An integrated circuit package having encapsulated therein a chip in accordance with claim 10, said package having external pins for connections to said integrated circuit on said chip, and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to an external pin of the package.

18. A method for the manufacture of an integrated circuit chip having an integrated circuit thereon with said integrated circuit comprising a microprocessor and a program read-only memory containing a program to be carried out by the microprocessor, the integrated circuit having at least one transmission contact pad enabling the transmission of addresses and data between the microprocessor and an electrically programmable memory which would be located external to the chip, at least one mode selection contact pad for selecting the mode of operation of the microprocessor, and a mode selection circuit to select one of two possible modes of operation of the microprocessor as a function of a signal present at said mode selection contact pad, the first mode of operation involving the connection of the microprocessor to an electrically programmable memory located external to the chip, the second mode of operation involving the connection of the microprocessor to said program read-only memory;

wherein said method comprises;

during a stage for the perfecting and finalizing of the circuits of a first version of the chip and programs to be contained in the read-only memory, the step of applying a specific logic level to said mode selection contact pad to place the microprocessor in said first mode of operation, and the step of causing said microprocessor to carry out at least one program contained in said electrically programmable memory located external to the chip wherein the microprocessor exchanges addresses and data with said electrically programmable memory through said transmission contact pad; and

during a stage of manufacturing the chip in a final version which differs from said first version only in the program content of the program read-only memory, the step of systematically applying to said mode selection contact pad a logic level complementary to said specific logic level, to thereby select the second mode of operation for said microprocessor.

19. A method in accordance with claim 18, further comprising the step, during said stage for the perfecting and finalizing, of encapsulating the first version of the chip in a package having a predetermined number of external pins;

and the step, during the stage of manufacturing the chip in a final version, of encapsulating the final version of the chip in a package having fewer external pins than said predetermined number of external pins, at least one of said transmission contact pad and said mode selection contact pad being not connected to an external pin in the package of the final version of the chip.

20. A method in accordance with claim 18, wherein said step of systematically applying to said mode selection contact pad a logic level complementary to said specific logic level is accomplished by connecting said mode selection contact pad through a resistive circuit element to a voltage supply terminal of the integrated circuit.

21. A method in accordance with claim 18, wherein said step of systematically applying to said mode selection contact pad a logic level complementary to said specific logic level is accomplished by connecting said mode selection contact pad through a transistor to a voltage supply terminal of the integrated circuit.

22. A method in accordance with claim 18, wherein the step of causing said microprocessor to carry out at least one program contained in said electrically programmable memory located external to the chip wherein the microprocessor exchanges addresses and data with said electrically programmable memory through said transmission contact pad comprises causing said microprocessor to carry out at least one program contained in said electrically programmable memory located external to the chip wherein the microprocessor exchanges addresses and data with said electrically programmable memory through first and second parallel/series converters and first and second series/parallel converters, said first parallel/series converter and said first series/parallel converter being connected between said microprocessor and said transmission contact pad, and said second parallel/series converter and said second series/parallel converter being located external to the chip and connected between said transmission contact pad and said electrically programmable memory.

23. A method in accordance with claim 18 wherein the chip further comprises a synchronizing contact pad, and wherein the method further comprises, during the stage for the perfecting and finalizing of the circuits of a first version of the chip and programs to be contained in the read-only memory, the step of transmitting a synchronizing signal to the synchronizing contact pad to define the nature of the signals at the transmission contact pad so as to distinguish between addresses and data.

24. A packaged integrated circuit comprising:

a program read-only memory, and a microprocessor core connected to execute programs from said read-only memory;

serial/parallel and parallel/serial interface logic, connected to provide communication of addresses and between at least one serial transmission contact pad and said microprocessor cores;

a mode selection circuit connected and configured to select between first and second possible modes of operation of said microprocessor as a function of a signal present at a mode selection contact pad,

said first mode of operation being the execution of a program which is interfaced to said microprocessor through said serial transmission contact pad, and

said second mode of operation being the execution of a program contained in said program read-only memory;

and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to any externally accessible connector of said package;

whereby said first mode of operation is inoperable in said packaged integrated circuit.

25. A packaged integrated circuit comprising:

a program read-only memory, and a microprocessor core connected to execute programs from said read-only memory;

serial/parallel and parallel/serial interface logic, connected to provide serial communication of addresses and data between at least one serial transmission contact pad and said microprocessor core, in accordance with signals provided at a synchronizing contact pad to distinguish between addresses and data;

a mode selection circuit connected and configured to select between first and second possible modes of operation of said microprocessor as a function of a signal present at a mode selection contact pad which is operatively connected to a voltage supply terminal,

said first mode of operation being the execution of a program which is interfaced to said microprocessor through said serial transmission contact pad, and

said second mode of operation being the execution of a program contained in said program read-only memory;

and wherein at least one of said transmission contact pad and said mode selection contact pad is not connected to any exterior portion of the package;

whereby said first mode of operation is inoperable in said packaged integrated circuit.

26. A method for developing integrated circuits which include programmable logic and read-only program memory, comprising the steps of:

(a) providing a first version of said integrated circuit, and connecting said programmable logic thereof, through a serial/parallel and parallel/serial interface, to fetch and execute program instructions from an off-chip memory;

(b) developing software for a given application, using the apparatus of step (a);

(c) manufacturing integrated circuits in a final version, which is identical to said first version except that said read-only program memory contains at least some software developed in said step (b), and packaging said integrated circuits in a configuration such that at least some connections necessary for said serial/parallel and parallel/serial interface are inaccessible.