Video hardware for protected, multiprocessing systems

• US 5,751,979 A
• Filed: 05/31/1995
• Issued: 05/12/1998
• Est. Priority Date: 05/31/1995
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Unisys Corporation
• Inventors: McCrory, Duane J.
• Primary Examiner(s): Bayerl, Raymond J.
• Assistant Examiner(s): dela Torre, Crescelle N.
• Application Number:
  US08/454,849
• Time in Patent Office: 1,077 Days
• Field of Search: 395/157, 395/158, 395/164, 395/165, 395/166, 395/343, 395/344, 395/509, 395/515, 395/516, 395/517, 345/118, 345/119, 345/120, 345/200
• US Class Current: 715/803
• CPC Class Codes: G09G 5/14 Display of multiple viewports

Abstract

A video controller that enables applications operating in a protected, multiprocessing system to update a video memory at native speeds. In this system and method, each application is assigned a separate physical address region that identifies an alias of an application'"'"'s window in the video memory. The separate physical address regions provide an addressing mechanism for an application to identify a referenced set of pixels sought to be accessed. A window mapping function within the video controller that performs only those portions of a video memory access request that references pixels contained within a visible portion of an application'"'"'s window as defined by priority, size and position information in a control structure.

Claims

1. A video controller in a protected, multiprocessing system comprising:

a) video memory for storing pixel information representing a plurality of application windows defined by a plurality of application programs to be displayed on a video monitor;

b) a control structure for storing priority, size and position information for a plurality of logical windows;

c) said logical windows corresponding to said application windows stored in said video memory,

d) said plurality of logical windows being defined by addresses in, and not contents of, separate physical address regions; and

e) window mapping hardware logic connected to said control structure for receiving video memory access requests from said plurality of application programs, comprising;

f) means for detecting logical window physical addresses in said video memory access request,

g) means for identifying the logical window to which said logical window physical addresses belong,

h) means for identifying the corresponding application window being accessed,

i) means for completing the allowable portions of said video memory access request that seeks to access pixels contained within by reference to logical window addresses that correspond to a visible portion of said corresponding application window, and

j) means for ignoring any portion of said video memory access request that seeks to access pixels by reference to those logical window addresses that do not correspond to a visible portion of said window stored in said video memory as defined by said priority, size and position information in said control structure.

2. The video controller of claim 1, wherein said size information comprises a height and width of said application window, and said position information comprises a x-y coordinate for one comer of said application window.

3. The video controller of claim 2, wherein said control structure also stores the mode of memory mapping of pixels.

4. The video controller of claim 1, wherein said window mapping hardware logic further comprises:

means for detecting a physical address in said video memory access request;

means for identifying a logical window based on said physical address alone, without needing to access data stored at said physical address; and

means for identifying a set of pixels within said identified logical window sought to be accessed.

5. The video controller of claim 4, wherein said window mapping hardware logic further comprises means for identifying, for each pixel in said set of pixels,

a row and column position within said identified logical window,

an actual display coordinate based on said row and column position and said position information for said identified logical window, and

a foreground window for said actual display coordinate, said foreground window equivalent to a logical window with the best priority.

6. The video controller of claim 5, wherein said window mapping hardware logic ignores portions of said video memory access request if:

said row or column position of said pixel is outside said logical window as defined by said size information in said control structure, or

said foreground window does not match said identified logical window.

7. The video controller of claim 1, further comprising a graphics accelerator that receives graphics commands posted by said plurality of applications in a plurality of command registers, and which evaluates said graphics commands and accesses said video memory based on said priority, size and position information in said control structure.

8. The video controller of claim 7, further comprising a plurality of first-in-first-out (FIFO) queues that receive video memory access requests from one of said plurality of applications.

9. The video controller of claim 1 wherein said video memory access requests define an address alias of a referenced pixel addressed via separate physical address regions, and each said physical address region defining a logical window corresponding to a window stored in said video memory.

10. The video controller of claim 9, wherein a physical address within said referenced addressed pixel comprises:

a first set of bits that map into said video memory; and

a second set of bits that identify said logical window.

11. The video controller of claim 10, wherein said control structure is indexed by said second set of bits that stores priority, size and position information for said logical windows.

12. The video controller of claim 11, further comprising means for evaluating said video memory access requests that ignores a portion of said video memory access request if said referenced pixel is not contained within a visible portion of a window as defined by said priority, size and position information in said control structure.

13. The video controller of claim 10, wherein said step of writing further comprises the steps of:

using said second set of bits as an index into a control structure;

retrieving priority, size and position information for said application'"'"'s window indexed by said second set of bits; and

identifying, based on said priority, size and position information, whether said pixel is not contained within a visible portion of said application'"'"'s window.

14. A method for controlling access to a video memory in a protected, multiprocessing system, the method comprising the steps of:

a) assigning a unique logical address for each pixel in said video memory, without requiring pixel data storage capabilities therewith, in a separate physical address region for each application that desires access to the video memory,

b) arranging the logical addresses within said separate physical address region in a sequence defining a logical window corresponding to an application window in the video memory;

c) storing priority, size and position information for each said logical window in a control structure;

d) accessing said pixel addresses in the control structure by using said logical address values; and

e) writing pixel data in a portion of said video memory in response to an access request from an application if a referenced pixel in said video memory access request is contained within a visible portion of said application'"'"'s window as defined by said priority, size and position information stored for each logical window in said control structure.

15. The method of claim 14, wherein said size information comprises a height and width of said application'"'"'s window, and said position information comprises a x-y coordinate for one comer of said application window.

16. The method of claim 15, wherein said step of storing further comprises the step of storing layout information that describes the mode of memory mapping of pixels.

17. The method of claim 14, further comprising the steps of:

detecting a physical address in said video memory access request;

identifying a logical window based on said physical address; and

identifying a set of pixels within said identified logical window sought to be accessed.

18. The method of claim 17, further comprising the step of identifying, for each pixel in said set of pixels,

a row and column position within said identified logical window,

an actual display coordinate based on said row and column position and said position information for said identified logical window, and

a foreground window for said actual display coordinate, said foreground window equivalent to a logical window with the highest priority.

19. The method of claim 18, wherein a portion of said video memory access request is ignored if:

said row or column position of said pixel is outside said logical window as defined by said size information in said control structure, or

said foreground window does not match said identified logical window.