Distributed processing memory chip with embedded logic having both data memory and broadcast memory
First Claim
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1. An integrated circuit memory chip having logic embedded thereon, comprising:
- a data memory, said data memory directly coupled through an input/output multiplexer to a data bus terminal;
a chip select terminal coupled to said data memory;
a broadcast memory, said broadcast memory directly coupled through said input/output multiplexer to said data bus terminal, and said broadcast memory not coupled to said chip select terminal, wherein said broadcast memory responds to a broadcast write by an external CPU;
an address bus directly coupled to both said data memory and said broadcast memory; and
a datapath coupled to both said data memory and said broadcast memory, said data path including circuitry for computation with data from said data memory, and a detector for receiving an external signal for initiating and terminating said computation.
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Abstract
Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data memory (202) by the embedded logic (206) with minimal handshaking with a remote CPU. In a functioning system, the memory chips are organized in a hierarchical manner and include address-associative memory systems.
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Citations
12 Claims
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1. An integrated circuit memory chip having logic embedded thereon, comprising:
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a data memory, said data memory directly coupled through an input/output multiplexer to a data bus terminal; a chip select terminal coupled to said data memory; a broadcast memory, said broadcast memory directly coupled through said input/output multiplexer to said data bus terminal, and said broadcast memory not coupled to said chip select terminal, wherein said broadcast memory responds to a broadcast write by an external CPU; an address bus directly coupled to both said data memory and said broadcast memory; and a datapath coupled to both said data memory and said broadcast memory, said data path including circuitry for computation with data from said data memory, and a detector for receiving an external signal for initiating and terminating said computation. - View Dependent Claims (2, 3, 4)
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5. A computer system, comprising:
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a central processing unit; a memory system, said memory system including a plurality of memory integrated circuits (ICs), each of said memory ICs including; a data memory, said data memory coupled to a data bus terminal; a chip select terminal coupled to said data memory for receiving a signal from said central processing unit; a broadcast memory, said broadcast memory coupled to said data bus terminal, and said broadcast memory not coupled to said chip select terminal, wherein the broadcast memories from more than one of said memory ICs respond simultaneously to a single broadcast write from said central processing unit; an address bus terminal directly coupled to said data memory and broadcast memory; a datapath coupled to both said data memory and said broadcast memory; and input/output circuitry for connecting said central processing unit and said memory system. - View Dependent Claims (6, 7, 8, 9, 10, 11, 12)
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Specification