Distributed processing memory chip with embedded logic having both data memory and broadcast memory

• US 5,751,987 A
• Filed: 05/04/1995
• Issued: 05/12/1998
• Est. Priority Date: 03/16/1990
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Smith, Derek J., Doddington, George R., Bean, Warren L., Aton, Thomas J., Mahant-Shetti, Shivaling S., Pawate, Basavaraj I., Harward, Mark G.
• Primary Examiner(s): Robertson, David L.
• Application Number:
  US08/434,885
• Time in Patent Office: 1,104 Days
• Field of Search: 395/425 MS, 395/431, 395/405, 365/230.05, 365/189.04, 365/189.08, 365/230.03, 365/238.5, 365/230.04
• US Class Current: 711/5
• CPC Class Codes: G06F 12/0646 Configuration or reconfiguration
• CPC Class Codes: G06F 15/7821 Tightly coupled to memory, e.g. computational memory, smart memory, processor in memory
• CPC Class Codes: G06F 9/3879 for non-native instruction execution, e.g. executing a command; for Java instruction set

Abstract

Memory chips with data memory (202), embedded logic (206) and broadcast memory (204) for two modes of operation are disclosed. A first mode of operation is the usual memory mode expected of a data RAM. The second mode of operation allows localized computation and/or processing of the data in data memory (202) by the embedded logic (206) with minimal handshaking with a remote CPU. In a functioning system, the memory chips are organized in a hierarchical manner and include address-associative memory systems.

Claims

1. An integrated circuit memory chip having logic embedded thereon, comprising:

a data memory, said data memory directly coupled through an input/output multiplexer to a data bus terminal;

a chip select terminal coupled to said data memory;

a broadcast memory, said broadcast memory directly coupled through said input/output multiplexer to said data bus terminal, and said broadcast memory not coupled to said chip select terminal, wherein said broadcast memory responds to a broadcast write by an external CPU;

an address bus directly coupled to both said data memory and said broadcast memory; and

a datapath coupled to both said data memory and said broadcast memory, said data path including circuitry for computation with data from said data memory, and a detector for receiving an external signal for initiating and terminating said computation.

2. The integrated circuit of claim 1 wherein said broadcast memory is addressable by an external source.

3. The integrated circuit of claim 1 wherein at least a portion of said data memory has a common address with said broadcast memory.

4. The memory chip of claim 1, wherein said data memory comprises an SRAM array and said broadcast memory comprises an SRAM array.

5. A computer system, comprising:

a central processing unit;

a memory system, said memory system including a plurality of memory integrated circuits (ICs), each of said memory ICs including;

a data memory, said data memory coupled to a data bus terminal;

a chip select terminal coupled to said data memory for receiving a signal from said central processing unit;

a broadcast memory, said broadcast memory coupled to said data bus terminal, and said broadcast memory not coupled to said chip select terminal, wherein the broadcast memories from more than one of said memory ICs respond simultaneously to a single broadcast write from said central processing unit;

an address bus terminal directly coupled to said data memory and broadcast memory;

a datapath coupled to both said data memory and said broadcast memory; and

input/output circuitry for connecting said central processing unit and said memory system.

6. The system of claim 5, further comprising:

a detector in each of said memories and coupled to said address bus terminal and said broadcast memory.

7. The computer system of claim 5, wherein

(a) said plurality of memories is hierarchically arranged.

8. The computer system of claim 5, wherein

(a) each memory of said plurality includes sparse distributed memory address and data circuitry.

9. The computer system of claim 5 wherein said broadcast memory is addressable by an external source.

10. The computer system of claim 5 wherein at least a portion of said data memory has a common address with said broadcast memory.

11. The computer system of claim 5 wherein said data path of each memory includes circuitry for computation using data from its associated memory and each memory further includes a detector for receiving a signal from said central processing unit for initiating and terminating said computation.

12. The computer system of claim 5, wherein said data memory comprises an SRAM array and said broadcast memory comprises an SRAM array.