Method and apparatus for performance optimization of integrated circuit designs

• US 5,752,002 A
• Filed: 06/12/1995
• Issued: 05/12/1998
• Est. Priority Date: 06/12/1995
• Status: Expired due to Fees

• Current Assignee: Sand Microelectronics, Inc. (Pharaoh Acquisition LLC)
• Original Assignee: Sand Microelectronics, Inc. (Pharaoh Acquisition LLC)
• Inventors: Deora, Ajit, Naidu, Anand, Arunarthi, Venkatesham
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/489,654
• Time in Patent Office: 1,065 Days
• Field of Search: 364/488-491, 364/578, 395/500
• US Class Current: 703/14
• CPC Class Codes: G06F 11/3457 Performance evaluation by simulation
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A method and apparatus are provided for optimizing performance of a computer system component design by performance analysis of a simulation of the design. The method of the present invention comprises providing the computer system component design to an analyzing apparatus and carrying out a simulation run of the design. During the simulation run, operation data is generated cycle by cycle, and the generated operation data is collected and stored in a log file. The log file is input to a parser and the operation data is sequentially parsed to produce parsed data. Statistical calculations are then performed on the parsed data, and the performance results are output to the designer in graphical form. The performance information can be used to enhance performance of the computer system component prior to its fabrication.

Claims

1. A method for optimizing performance of a computer system component design by analyzing simulation of the component design, the method comprising the steps of:

(a) providing the computer system component design to a simulation apparatus;

(b) simulating operation of the component design by performing a plurality of transactions, and generating an operation data set for each transaction;

(c) collecting and storing the operation data set from each transaction;

(d) sequentially parsing the stored operation data sets to produce parsed data by inputting the stored operation data set and a user configuration file, and parsing the operation data set based on the user configuration file to produce the parsed data, the user configuration file capable of being edited by the user to enable or disable user designated data types;

(e) performing a statistical analysis of the parsed data; and

(f) outputting performance information in graphical, text, or tabular form, in response to the statistical analysis,

whereby the performance information can be used to improve performance of the computer system component prior to its fabrication.

2. The method of claim 1, wherein the step of sequentially parsing comprises steps of (i) transaction extraction, (ii) transaction analysis, (iii) transaction filtering, and (iv) global data structure updating, wherein steps (i)-(iv) are repeated on the stored operation data set for each transaction.

3. The method of claim 1, wherein the step of outputting performance information further comprises categorizing the performance information into user designated groups to provide performance data specific to the component design.

4. The method of claim 2, wherein:

(a) the step of transaction extraction comprises extracting information from the stored operation data set for a transaction and storing the extracted information in a first data structure;

(b) the step of transaction analysis comprises collecting and calculating predetermined information from the first data structure, and storing the predetermined information in a second data structure;

(c) the step of transaction filtering comprises comparing the information in the second data structure with user specified data; and

(d) the step of global data structure updating comprises updating a statistical global data structure and a performance global data structure with the information from the second data structure if a match occurred in the comparing step,

wherein the parsed data comprises the updated statistical global data structure and the updated performance global data structure.

5. The method of claim 1, further comprising outputting error information associated with any errors occurring during the simulation.

6. The method of claim 1, wherein the step of simulating operation of the component design includes performing at least about 1000 transactions.

7. The method of claim 1, wherein the step of outputting performance data in graphical form comprises outputting the performance data in a tabular, graph or chart form.

8. A method for optimizing performance of a computer system component design by analyzing simulation of the component design, the method comprising the steps of:

(a) providing a computer system component design to a simulation apparatus;

(b) running a simulation of the component design, the simulation executing a plurality of transactions, each transaction occurring over a plurality of clock cycles, and the simulation generating sets of transaction data during one or more clock cycles;

(c) collecting the sets of transaction data for the clock cycles and storing the sets of transaction data in a log file;

(d) inputting the log file and a configuration file to a parser;

(e) based on the log file and the configuration file, sequentially parsing all the transaction data stored in the log file and providing output data, the parsing including steps of (i) transaction extraction, (ii) transaction analysis, (iii) transaction filtering, and (iv) data structure updating, wherein steps (i)-(iv) are repeated for each transaction stored in the log file; and

(f) presenting the output data as feedback to a designer in graphical, text, or tabular form.

9. The method of claim 8, further comprising selecting a default configuration file or a user designated configuration as the configuration file to be input to the parser.

10. The method of claim 8, wherein:

(a) the step of transaction extraction comprises extracting an entire transaction from a transaction start point to a transaction endpoint and storing the extracted information in a first data structure;

(b) the step of transaction analysis comprises collecting and calculating predetermined information from the first data structure, and storing the predetermined information in a second data structure;

(c) the step of transaction filtering comprises comparing the information in the second data structure with user specified data; and

(d) the step of data structure updating comprises updating a statistical global data structure and a performance global data structure with the information from the second data structure if a match occurred in the comparing step,

wherein the output data comprises the updated statistical global data structure and the updated performance global data structure.

11. The method of claim 10, wherein in step (i), the transaction endpoint comprises an abort signal, a retry signal, a disconnect signal, and a completion signal.

12. The method of claim 8, wherein the step of presenting the output data further comprises categorizing the output data into user designated groups and separately displaying the categories of output data.

13. The method of claim 8, wherein the step of presenting the output data comprises categorizing and displaying (i) statistical data, (ii) performance data, (iii) timing data, and (iv) error data.

14. A system for optimizing performance of a computer system component design by analyzing simulation of the component design, the system comprising:

(a) an integrated circuit design module;

(b) at least one functional model capable of simulating operation of a computer system component;

(c) a bus for connecting the integrated circuit design module to the functional model, the integrated circuit design module designed to perform an application specific function;

(d) a performance analyzer interconnected to the bus for monitoring one-or more signals exchanged between integrated circuit design module and a selected functional model, and for parsing the signals to create performance reports, the performance analyzer comprising a monitoring means for logging the signals into a log file, and a parsing means for parsing through the signals in the log file to create the performance reports; and

(e) a graphical user interface connected to the performance analyzer for outputting the performance reports in human readable form as feedback to a component designer,

whereby the performance reports can be used by the component designer to optimize the component design prior to fabrication of the component.

15. The system of claim 14, further comprising a plurality of buses for connecting the integrated circuit design module to a plurality of functional models.

16. The system of claim 14, wherein the functional models include bus models, CPU models, memory models, network interface models, and disk interface models, and wherein the performance analyzer is capable of being interconnected to the bus between the integrated circuit design and any one of the models.