Configuration emulation of a programmable logic device

• US 5,752,006 A
• Filed: 02/29/1996
• Issued: 05/12/1998
• Est. Priority Date: 01/31/1996
• Status: Expired due to Term

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Baxter, Glenn A.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/613,785
• Time in Patent Office: 803 Days
• Field of Search: 395/500, 364/488, 364/489, 364/490, 364/578, 326/41, 326/39, 326/38, 326/37
• US Class Current: 703/14
• CPC Class Codes: G06F 30/30 Circuit design
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

A configuration emulation circuit generates configuration signals to emulate a programmable Logic Device (PLD) in a configuration timing relationship and a configuration protocol relationship between a programming circuit and the PLD. The circuit includes a first circuit to emulate the PLD in the configuration timing relationship. The circuit also includes a second circuit to emulate the PLD in the configuration protocol relationship. The second circuit is coupled to receive a configuration mode signal and is responsive to the configuration mode signal.

Claims

1. A circuit for emulating a configuration timing relationship and a configuration protocol relationship between a programmable Logic Device (PLD) and a programming circuit, said programming circuit using a configuration mode signal to said PLD to establish said configuration timing relationship and said configuration protocol relationship, said circuit comprising:

a first circuit to emulate said PLD in said configuration timing relationship; and

a second circuit to emulate said PLD in said configuration protocol relationship, said second circuit being coupled to said first circuit and being coupled to receive said configuration mode signal, and wherein said second circuit is responsive to said configuration mode signal, said second circuit further configured to emulate said PLD in a second configuration protocol relationship responsive to a second configuration mode signal.

2. The circuit of claim 1 wherein said first circuit includes a power stable circuit and a power on reset circuit, said power stable circuit indicating a stable power supply to said circuit, said power on reset circuit to reset said circuit responsive to said power stable circuit.

3. The circuit of claim 1 wherein said second circuit includes a PLD family type and a PLD device type specified configuration protocol emulation circuit, said PLD family type and said PLD device type defining a set of configuration modes to be emulated and a set of configuration programming characteristics.

4. The circuit of claim 3 wherein said set of configuration programming characteristics includes a number of bits per frame characteristic and a number of frames characteristic.

5. The circuit of claim 3 wherein said family type is included in and is defined by said device type.